C8051F018-GQ Silicon Laboratories Inc, C8051F018-GQ Datasheet - Page 148

• Manufacturer Part Number: C8051F018-GQ
• Description: IC 8051 MCU 16K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F018r

Specifications of C8051F018-GQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 2.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1197

19.1.
The Data Register in the Boundary Scan path is an 87-bit shift register. The Boundary DR provides control and
observability of all the device pins as well as the SFR bus and Weak Pullup feature via the EXTEST and SAMPLE
commands.
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
23,25,27,29,
31,33,35,37
24,26,28,30,
32,34,36,38
39,41,43,45,
47,49,51,53
40,42,44,46,
48,50,52,54
55,57,59,61,
63,65,67,69
56,58,60,62,
64,66,68,70
71,73,75,77,
79,81,83,85
72,74,76,78,
80,82,84,86
12-19
4-11
Bit
20
21
22
0
1
2
3
Boundary Scan
Action
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Capture
Update
Target
Reset Enable from MCU
Reset Enable to /RST pin
Reset input from /RST pin
Reset output to /RST pin
External Clock from XTAL1 pin
Not used
Weak pullup enable from MCU
Weak pullup enable to Port Pins
SFR Address Bus bit from CIP-51 (e.g. Bit4=SFRA0, Bit5=SFRA1…)
SFR Address Bus bit to SFR Address Bus (e.g. Bit4=XSFRA0, Bit5=XSFRA1)
SFR Data Bus bit read from SFR (e.g. Bit12=SFRD0, Bit13=SFRD1…)
SFR Data Bus bit written to SFR (e.g. Bit12=SFRD0, Bit13=SFRD1…)
SFR Write Strobe from CIP-51
SFR Write Strobe to SFR Bus
SFR Read Strobe from CIP-51
SFR Read Strobe to SFR Bus
SFR Read/Modify/Write Strobe from CIP-51
SFR Read/Modify/Write Strobe to SFR Bus
P0.n output enable from MCU (e.g. Bit23=P0.0, Bit25=P0.1, etc.)
P0.n output enable to pin (e.g. Bit23=P0.0oe, Bit25=P0.1oe, etc.)
P0.n input from pin (e.g. Bit24=P0.0, Bit26=P0.1, etc.)
P0.n output to pin (e.g. Bit24=P0.0, Bit26=P0.1, etc.)
P1.n output enable from MCU (e.g. Bit39=P1.0, Bit41=P1.1, etc.)
P1.n output enable to pin (e.g. Bit39=P1.0oe, Bit41=P1.1oe, etc.)
P1.n input from pin (e.g. Bit40=P1.0, Bit42=P1.1, etc.)
P1.n output to pin (e.g. Bit40=P1.0, Bit42=P1.1, etc.)
P2.n output enable from MCU (e.g. Bit55=P2.0, Bit57=P2.1, etc.)
P2.n output enable to pin (e.g. Bit55=P2.0oe, Bit57=P2.1oe, etc.)
P2.n input from pin (e.g. Bit56=P2.0, Bit58=P2.1, etc.)
P2.n output to pin (e.g. Bit56=P2.0, Bit58=P2.1, etc.)
P3.n output enable from MCU (e.g. Bit71=P3.0, Bit73=P3.1, etc.)
P3.n output enable to pin (e.g. Bit71=P3.0oe, Bit73=P3.1oe, etc.)
P3.n input from pin (e.g. Bit72=P3.0, Bit74=P3.1, etc.)
P3.n output to pin (e.g. Bit72=P3.0, Bit74=P3.1, etc.)
Table 19.1. Boundary Data Register Bit Definitions
Rev. 1.2
C8051F018
C8051F019
148