C8051F018-GQ Silicon Laboratories Inc, C8051F018-GQ Datasheet - Page 5

• Manufacturer Part Number: C8051F018-GQ
• Description: IC 8051 MCU 16K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F018r

Specifications of C8051F018-GQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 2.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1197

16. UART.................................................................................................................................. 113
17. TIMERS ............................................................................................................................. 121
18. PROGRAMMABLE COUNTER ARRAY..................................................................... 137
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C8051F018
C8051F019
15.3. Serial Clock Timing...............................................................................................................................109
Figure 15.4. Data/Clock Timing Diagram .......................................................................................................109
15.4. SPI Special Function Registers..............................................................................................................110
Figure 15.5. SPI0CFG: SPI Configuration Register........................................................................................110
Figure 15.6. SPI0CN: SPI Control Register ....................................................................................................111
Figure 15.7. SPI0CKR: SPI Clock Rate Register............................................................................................112
Figure 15.8. SPI0DAT: SPI Data Register ......................................................................................................112
Figure 16.1. UART Block Diagram ................................................................................................................113
16.1. UART Operational Modes.....................................................................................................................114
Table 16.1. UART Modes ...............................................................................................................................114
Figure 16.2. UART Mode 0 Interconnect........................................................................................................114
Figure 16.3. UART Mode 0 Timing Diagram.................................................................................................114
Figure 16.4. UART Mode 1 Timing Diagram.................................................................................................115
Figure 16.5. UART Modes 1, 2, and 3 Interconnect Diagram ........................................................................116
Figure 16.6. UART Modes 2 and 3 Timing Diagram......................................................................................117
16.2. Multiprocessor Communications ...........................................................................................................118
Figure 16.7. UART Multi-Processor Mode Interconnect Diagram .................................................................118
Table 16.2. Oscillator Frequencies for Standard Baud Rates ..........................................................................119
Figure 16.8. SBUF: Serial (UART) Data Buffer Register...............................................................................119
Figure 16.9. SCON: Serial Port Control Register............................................................................................120
17.1. Timer 0 and Timer 1 ..............................................................................................................................121
Figure 17.1. T0 Mode 0 Block Diagram..........................................................................................................122
Figure 17.2. T0 Mode 2 Block Diagram..........................................................................................................123
Figure 17.3. T0 Mode 3 Block Diagram..........................................................................................................124
Figure 17.4. TCON: Timer Control Register...................................................................................................125
Figure 17.5. TMOD: Timer Mode Register.....................................................................................................126
Figure 17.6. CKCON: Clock Control Register................................................................................................127
Figure 17.7. TL0: Timer 0 Low Byte ..............................................................................................................128
Figure 17.8. TL1: Timer 1 Low Byte ..............................................................................................................128
Figure 17.9. TH0: Timer 0 High Byte .............................................................................................................128
Figure 17.10. TH1: Timer 1 High Byte ...........................................................................................................128
17.2. Timer 2 ..................................................................................................................................................129
Figure 17.11. T2 Mode 0 Block Diagram........................................................................................................130
Figure 17.12. T2 Mode 1 Block Diagram........................................................................................................131
Figure 17.13. T2 Mode 2 Block Diagram........................................................................................................132
Figure 17.14. T2CON: Timer 2 Control Register............................................................................................133
Figure 17.15. RCAP2L: Timer 2 Capture Register Low Byte ........................................................................134
Figure 17.16. RCAP2H: Timer 2 Capture Register High Byte .......................................................................134
Figure 17.17. TL2: Timer 2 Low Byte ............................................................................................................134
Figure 17.18. TH2: Timer 2 High Byte ...........................................................................................................134
17.3. Timer 3 ..................................................................................................................................................135
Figure 17.19. Timer 3 Block Diagram.............................................................................................................135
Figure 17.20. TMR3CN: Timer 3 Control Register ........................................................................................135
Figure 17.21. TMR3RLL: Timer 3 Reload Register Low Byte ......................................................................136
Figure 17.22. TMR3RLH: Timer 3 Reload Register High Byte .....................................................................136
Figure 17.23. TMR3L: Timer 3 Low Byte ......................................................................................................136
Figure 17.24. TMR3H: Timer 3 High Byte .....................................................................................................136
Figure 18.1. PCA Block Diagram ...................................................................................................................137
18.1. Capture/Compare Modules ....................................................................................................................138
Table 18.1. PCA0CPM Register Settings for PCA Capture/Compare Modules .............................................138
Figure 18.2. PCA Interrupt Block Diagram.....................................................................................................138
Rev. 1.2