C8051F018-GQ Silicon Laboratories Inc, C8051F018-GQ Datasheet - Page 25

• Manufacturer Part Number: C8051F018-GQ
• Description: IC 8051 MCU 16K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F018r

Specifications of C8051F018-GQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 2.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1197

5. ADC
The ADC subsystem consists of a 9-channel configurable analog multiplexer (AMUX) and a 100ksps, 10-bit
successive-approximation-register ADC with integrated track-and-hold and programmable window detector (see
block diagram in Figure 5.1).
configurable under software control via the Special Function Register’s shown in Figure 5.1. The ADC subsystem
(ADC, track-and-hold and PGA) is enabled only when the ADCEN bit in the ADC Control register (ADC0CN,
Figure 5.7) is set to 1. The ADC subsystem is in low power shutdown when this bit is 0. The Bias Enable bit
(BIASE) in the REF0CN register (see Figure 7.2) must be set to 1 in order to supply bias to the ADC.
5.1.
Figure 5.3). AMUX input pairs can be programmed to operate in either the differential or single-ended mode. This
allows the user to select the best measurement technique for each input channel, and even accommodates mode
changes “on-the-fly”. The AMUX defaults to all single-ended inputs upon reset. There are two registers associated
with the AMUX: the Channel Selection register AMX0SL (Figure 5.5), and the Configuration register AMX0CF
(Figure 5.4). The table in Figure 5.5 shows AMUX functionality by channel for each possible configuration.
25
Eight of the AMUX channels are available for external measurements while the ninth channel is internally
C8051F018
C8051F019
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Analog Multiplexer
connected to an on-board temperature sensor (temperature transfer function is shown in
SENSOR
AGND
TEMP
AMX0CF
ADC0GTH
+
+
+
+
-
-
-
-
AMUX
(SE or
9-to-1
DIFF)
Figure 5.1. 10-Bit ADC Functional Block Diagram
The AMUX, PGA, Data Conversion Modes, and Window Detector are all
AMX0SL
ADC0GTL
Rev. 1.2
ADC0CF
ADC0LTH
ADCEN
ADC
10-Bit
AV+
SAR
ADC0CN
ADC0LTL
10
20
10
COMB
LOGIC
ADWINT