PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 96

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
REGISTER 6-1:
DS61143C-page 94
Legend:
R = Readable bit
U = Unimplemented bit
bit 31-27
bit 26
bit 25-21
bit 20
bit 19
bit 18
bit 17
bit 16
bit 15-7
bit 31
bit 23
bit 15
bit 7
r-x
r-x
r-x
r-x
—
—
—
—
Reserved: Maintain as ‘0’; ignore read
BMXCHEDMA: BMX PFM Cacheability for DMA Accesses bit
1 = Enable program Flash memory (data) cacheability for DMA accesses
0 = Disable program Flash memory (data) cacheability for DMA accesses
Reserved: Maintain as ‘0’; ignore read
BMXERRIXI: Enable Bus Error from IXI bit
1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
BMXERRICD: Enable Bus Error from ICD Debug Unit bit
1 = Enable bus error exceptions for unmapped address accesses initiated from ICD
0 = Disable bus error exceptions for unmapped address accesses initiated from ICD
BMXERRDMA: Bus Error from DMA bit
1 = Enable bus error exceptions for unmapped address accesses initiated from DMA
0 = Disable bus error exceptions for unmapped address accesses initiated from DMA
BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access
BMXERRIS: Bus error from CPU Instruction Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction
Reserved: Maintain as ‘0’; ignore read
BMXWS-
R/W-1
(requires cache to have data caching enabled)
(hits are still read from the cache, but misses do not update the cache)
access
access
DRM
r-x
r-x
r-x
—
—
—
BMXCON: BUS MATRIX CONFIGURATION REGISTER
W = Writable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r-x
r-x
r-x
r-x
—
—
—
—
BMXERRIXI
R/W-1
Preliminary
r-x
r-x
r-x
—
—
—
P = Programmable bit
BMXER-
R/W-1
RICD
r-x
r-x
r-x
—
—
—
CHEDMA
ERRDMA
R/W-0
R/W-1
R/W-0
BMX-
BMX-
r-x
—
© 2008 Microchip Technology Inc.
BMXARB<2:0>
r = Reserved bit
ERRDS
R/W-1
R/W-0
BMX-
r-x
r-x
—
—
BMXERRIS
R/W-1
R/W-0
bit 24
bit 16
bit 8
bit 0
r-x
r-x
—
—