PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 171

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.4
When the MVEC (INTCON<12>) bit is ‘1’, the interrupt
controller operates in Multi-Vector mode. In this mode,
the CPU vectors to the unique address for each vector
number. Each vector is located at a specific offset, with
respect to a base address specified by the EBase reg-
ister in the CPU. The individual vector address offset is
determined by the vector space that is specified by the
VS bits in the IntCtl register. (The IntCtl register is
located in the CPU; refer to Section 2.0 "PIC32MX
MCU" of this manual for more information.)
EXAMPLE 8-2:
© 2008 Microchip Technology Inc.
/*
*/
Set the CP0 registers for multi-vector interrupt
Place EBASE at 0xBD000000 and Vector Spacing to 32 bytes
This code example uses MPLAB C32 intrinsic functions to access CP0 registers.
Check your compiler documentation to find equivalent functions or use inline assembly
unsigned int temp;
asm(“di”);
temp = _CP0_GET_STATUS();
temp |= 0x00400000;
_CP0_SET_STATUS(temp);
_CP0_SET_EBASE(0xBD000000);
_CP0_SET_INTCTL(0x00000020);
temp = _CP0_GET_CAUSE();
temp |= 0x00800000;
_CP0_SET_CAUSE(temp);
temp = _CP0_GET_STATUS();
temp &= 0xFFBFFFFD;
_CP0_SET_STATUS(temp);
INTCONSET = 0x1000;
asm(“ie”);
Multi-Vector Mode
MULTI-VECTOR MODE INITIALIZATION
// Disable all interrupts
// Get Status
// Set BEV bit
// Update Status
// Set an EBase value of 0xBD000000
// Set the Vector Spacing to non-zero value
// Get Cause
// Set IV
// Update Cause
// Get Status
// Clear BEV and EXL
// Update Status
// Set MVEC bit
// Enable all interrupts
Preliminary
To configure the CPU in Multi-Vector mode, the follow-
ing CPU registers (IntCtl, Cause, and Status) and the
INTCON register must be configured as follows:
• EBase ≠ 00000
• VS (IntCtl<9:5>) ≠ 00000
• IV (Cause<23>) = 1
• EXL (Status<1>) = 0
• BEV (Status<22>) = 0
• MVEC (INTCON<12>) = 1
• IE (Status<0>) = 1
PIC32MX3XX/4XX
DS61143C-page 169