PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 496

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
22.2
This section will describe the operation the A/D con-
verter, the steps required to configure the converter,
describe the special feature of the module, and provide
examples of ADC configuration with timing diagrams
and charts showing the expected output of the
converter.
22.2.1
Analog sampling consists of two steps: acquisition and
conversion (see Figure 22-2). During acquisition the
analog input pin is connected to the Sample and Hold
Amplifier (SHA). After the pin has been sampled for a
sufficient period, the sample voltage is equivalent to the
input, the pin is disconnected from the SHA to provide
a stable input voltage for the conversion process. The
conversion process then converts the analog sample
voltage to a binary representation.
An overview of the ADC is presented in Figure 22-1.
The 10-bit A/D converter has a single SHA. The SHA is
connected to the analog input pins via the analog input
MUXs, MUX A and MUX B. The analog input MUXs are
controlled by the AD1CHS register. There are two sets
of MUX control bits in the AD1CHS register. These two
sets of control bits allow the two different analog input
to be independently controlled. The A/D converter can
optionally switch between MUX A and MUX B configu-
rations between conversions. The A/D converter can
also optionally scan through a series of analog inputs
using a single MUX.
FIGURE 22-2:
DS61143C-page 494
ADC Operation, Terminology and
Conversion Sequence
OVERVIEW OF OPERATION
ADC SAMPLE/CONVERSION SEQUENCE
SHA is connected to the analog input pin for sampling.
Acquisition Time
ADC Total Sample Time
SHA is disconnected from input and holds the signal.
A/D conversion is started by the conversion trigger source.
A/D Conversion Time
Preliminary
Acquisition time can be controlled manually or auto-
matically. The acquisition time may be started manually
by setting the SAMP bit (AD1CON1<1>), and ended
manually by clearing the SAMP in the user software.
The acquisition time may be started automatically by
the A/D converter hardware and ended automatically
by a conversion trigger source. The acquisition time is
set by the SAMC bits (AD1CON3<12:8>). The SHA
has a minimum acquisition period. Refer to the device
data sheet for acquisition time specifications
Conversion time is the time required for the A/D con-
verter to convert the voltage held by the SHA. The A/D
converter requires one ADC clock cycle (T
vert each bit of the result, plus two additional clock
cycles. Therefore, a total of 12 T
to perform the complete conversion. When the
conversion time is complete, the result is written into
one
(ADC1BUF0...ADC1BUFF).
The sum of the acquisition time and the A/D conver-
sion time provides the total sample time (refer to
Figure 22-2). There are multiple input clock options
for the A/D converter that are used to create the T
clock. The user must select an input clock option that
does not violate the minimum T
The sampling process can be performed once, period-
ically, or based on a trigger as defined by the module
configuration.
A/D conversion complete, result is written into the
ADC result buffer.
Optionally generate interrupt.
of
the
16
© 2008 Microchip Technology Inc.
ADC
AD
AD
specification.
cycles are required
result
AD
registers
) to con-
AD