PIC32MX440F512H-80I/PT Microchip Technology, PIC32MX440F512H-80I/PT Datasheet - Page 392

• Manufacturer Part Number: PIC32MX440F512H-80I/PT
• Description: IC PIC MCU FLASH 512K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F512H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 51
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC32MX3XX/4XX
17.2.4.1
This Framed SPI mode is enabled by setting bits
MSTEN (SPIxCON<5>) and FRMEN (SPIxCON<31>)
to ‘1’, and bit FRMSYNC (SPIxCON<30>) to ‘0’. In this
mode, the serial clock will be output continuously at the
SCKx pin, regardless of whether the module is
transmitting. When SPIxBUF is written, the SSx pin will
be driven active, high or low depending on bit FRMPOL
(SPIxCON<29>), on the next transmit edge of the
SCKx clock. The SSx pin will be active for one SCKx
clock cycle. The module will start transmitting data on
the same or on the next transmit edge of the SCKx,
depending on the SPIFE (SPIxCON<17>) setting, as
shown in Figure 17-6. A connection diagram indicating
signal directions for this operating mode is shown in
Figure 17-5.
The SCK, SDO and SSx pins are outputs, the SDI pin
is an input. Setting the control bit, DISSDO
(SPIxCON<12>), disables transmission at the SDO pin
if Receive Only mode of operation is desired.
Refer to Table 17-7.
The SDI (input) must be configured to properly sample
the data received from the slave device by configuring
the sample bit, SMP (SPIxCON<9>).
In Master mode, the SCK clock edge and polarity must
be configured properly for the master and slave device
to correctly transfer data synchronously.
Refer to timing diagram shown in Figure 17-3 to deter-
mine the appropriate settings.
17.2.4.2
The following bits must be configured as shown for the
Master mode of operation when configuring the
SPIxCON register:
• Enable Master Mode –
• Enable Framed SPI support –
• Select SSx pin as Frame Master (output) –
The remaining bits are shown with example
configurations and may be configured as desired:
• Enable module control of SDO pin –
• Configure SCK clock polarity to Idle high –
• Configure SCK clock edge transition from Idle to
• Select SSx active-low pin polarity –
• Select 16-bit data width –
DS61143C-page 390
active – CKE (SPIxCON<8>) = 0
MSTEN (SPIxCON<5>) = 1
FRMEN (SPIxCON<31>) = 1
FRMSYNC(SPIxCON<30>) = 0
SDO (SPIxCON<12>) = 0
CKP (SPIxCON<6>) = 1
FRMPOL (SPIxCON<29>) = 0
MODE<32,16> (SPIxCON<11:10>) = 01
SPI Master Mode and Frame Master
Mode Operations
Master SPIxCON Configuration
Preliminary
• Sample data input at middle – SMP
• Enable SPI module when CPU Idle – SIDL
17.2.4.3
The following steps are used to set up the SPI module
for the Master mode of operation:
1.
2.
3.
4.
5.
6.
7.
(SPIxCON<9>) = 0
(SPIxCON<13>) = 0
Note 1: The user must turn off the SPI device
If interrupts are used, disable the SPI interrupts
in the respective IEC0/1 register.
Stop and reset the SPI module by clearing the
ON bit.
Clear the receive buffer.
If using interrupts, the following additional steps
are performed:
• Clear the SPIx interrupt flags/events in the
• Set the SPIx interrupt enable bits in the
• Write the SPIx interrupt priority and subprior-
Clear the SPIROV bit (SPIxSTAT<6>).
Write the selected configuration settings to the
SPIxCON register.
Enable SPI operation by setting the ON bit
(SPIxCON<15>).
respective IFS0/1 register.
respective IEC0/1 register.
ity bits in the respective IPC5/7 register.
2: The SPIxSR register cannot be written
prior to changing the CKE or CKP bits.
Otherwise, the behavior of the device is
not ensured.
into directly by the user. All writes to the
SPIxSR register are performed through
the SPIxBUF register.
Framed Master Mode Initialization
© 2008 Microchip Technology Inc.