PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet - Page 419

• Manufacturer Part Number: PIC18F6527-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6527-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 28-23:
TABLE 28-24: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 28-24:
TABLE 28-25: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
 2004 Microchip Technology Inc.
120
121
122
125
126
Param
Param.
No.
No.
Note:
CKx/TXx
DTx/RXx
T
T
T
Note:
DTx/RXx
CKx/TXx
T
T
CK
CKRF
Symbol
DTRF
Symbol
CK
DT
pin
pin
H2
L2
V2
Refer to Figure 28-5 for load conditions.
DT
pin
pin
DTL
CKL
V SYNC XMIT (MASTER and SLAVE)
Refer to Figure 28-5 for load conditions.
Clock High to Data Out Valid
Clock Out Rise Time and Fall Time
(Master mode)
Data Out Rise Time and Fall Time
SYNC RCV (MASTER and SLAVE)
Data Hold before CKx ↓ (DTx hold time)
Data Hold after CKx ↓ (DTx hold time)
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
120
Characteristic
121
Characteristic
125
Preliminary
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
121
126
PIC18F8722 FAMILY
Min
10
15
Min
Max
—
—
—
—
—
—
—
—
Units
Max
ns
ns
100
40
20
50
20
50
122
Units
ns
ns
ns
ns
ns
ns
DS39646B-page 417
Conditions
V
V
V
Conditions
DD
DD
DD
= 2.0V
= 2.0V
= 2.0V