PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet - Page 319

• Manufacturer Part Number: PIC18F6527-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6527-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.5
The user program memory is divided into four blocks
for
PIC18F6622/8622 devices, six blocks for PIC18F6627/
8627 devices and eight blocks for PIC18F6722/8722
devices. One of these is a Boot Block of 2, 4 or
8 Kbytes. The remainder of the memory is divided into
blocks on binary boundaries.
FIGURE 25-5:
 2004 Microchip Technology Inc.
Note:
000000h
01FFFFh
200000h
3FFFFFh
PIC18F6527/8527
*
Sizes of memory areas are not to scale.
Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L.
Program Verification and
Code Protection
Unimplemented
Code Memory
Configuration
Read as ‘0’
and ID
Space
CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F8722 FAMILY
devices,
five
(PIC18FX722)
128 Kbytes
Boot Block
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
blocks
Preliminary
for
Unimplemented
(PIC18FX627)
96 Kbytes
Boot Block
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 25-5 shows the program memory organization for
48, 64, 96 and 128-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 25-3.
PIC18F8722 FAMILY
MEMORY SIZE/DEVICE
Unimplemented
(PIC18FX622)
64 Kbytes
Boot Block
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
Unimplemented
(PIC18FX527)
48 Kbytes
Boot Block
Read ‘0’s
Block 0
Block 1
Block 2
DS39646B-page 317
000000h
0007FFh* or
000FFFh* or
001FFFh*
000800h* or
001000h* or
002000h*
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
010000h
013FFFh
014000h
017FFFh
018000h
01BFFFh
01C000h
01FFFFh
Address
Range