PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet
PIC18F6527-I/PT
Specifications of PIC18F6527-I/PT
Available stocks
Related parts for PIC18F6527-I/PT
PIC18F6527-I/PT Summary of contents
Page 1
... Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology 2004 Microchip Technology Inc. PIC18F8722 Family Data Sheet 64/80-Pin, 1-Mbit, Preliminary DS39646B ...
Page 2
... PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... External Memory Interface (PIC18F8527/8622/8627/8722 only): • Address capability Mbytes • 8-bit or 16-bit interface • 8, 12, 16 and 20-bit Address modes Program Memory Device Flash # Single-Word SRAM (bytes) Instructions (bytes) PIC18F6527 48K 24576 3936 PIC18F6622 64K 32768 3936 PIC18F6627 96K 49152 3936 PIC18F6722 ...
Page 4
... RG4/CCP5/P1D RF7/SS1 11 RF6/AN11 12 RF5/AN10/CV REF 13 RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX configuration bit. DS39646B-page PIC18F6527 42 PIC18F6622 41 PIC18F6627 40 PIC18F6722 Preliminary RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC V SS OSC2/CLKO/RA6 OSC1/CLKI/RA7 V DD RB7/KBI3/PGD RC5/SDO1 RC4/SDI1/SDA1 RC3/SCK1/SCL1 RC2/ECCP1/P1A 2004 Microchip Technology Inc. ...
Page 5
... RF3/AN8 17 RF2/AN7/C1OUT 18 (2) RH7/AN15/P1B 19 (2) RH6/AN14/P1C Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX configuration bit and Processor mode settings. 2: P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX configuration bit. 2004 Microchip Technology Inc. PIC18F8722 FAMILY PIC18F8527 52 PIC18F8622 ...
Page 6
... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 429 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 429 Index .................................................................................................................................................................................................. 431 On-Line Support................................................................................................................................................................................. 443 Systems Information and Upgrade Hot Line ...................................................................................................................................... 443 Reader Response .............................................................................................................................................................................. 444 PIC18F8722 Family Product Identification System............................................................................................................................ 445 DS39646B-page 4 Preliminary 2004 Microchip Technology Inc. ...
Page 7
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Preliminary DS39646B-page 5 ...
Page 8
... PIC18F8722 FAMILY NOTES: DS39646B-page 6 Preliminary 2004 Microchip Technology Inc. ...
Page 9
... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F6527 • PIC18LF6527 • PIC18F6622 • PIC18LF6622 • PIC18F6627 • PIC18LF6627 • PIC18F6722 • PIC18LF6722 • PIC18F8527 • PIC18LF8527 • PIC18F8622 • PIC18LF8622 • PIC18F8627 • PIC18LF8627 • ...
Page 10
... Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 28.0 “Electrical Characteristics” for time-out periods. Preliminary 2004 Microchip Technology Inc. ...
Page 11
... Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1. Flash program memory (48 PIC18F6527/8527 devices, 64 Kbytes for PIC18F6622/8622 devices, 96 Kbytes PIC18F6627/8627 devices and 128 Kbytes for PIC18F6722/8722). 2. A/D channels (12 for 64-pin devices, 16 for 80-pin devices) ...
Page 12
... POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, Stack Full, Stack Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes Yes Yes 75 Instructions; 75 Instructions; 83 with Extended 83 with Extended Instruction Set enabled 80-pin TQFP 80-pin TQFP 2004 Microchip Technology Inc. ...
Page 13
... FIGURE 1-1: PIC18F6527/6622/6627/6722 (64-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory (48/64/96/128 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> Instruction Decode and Control (3) Internal OSC1 Oscillator Block (3) OSC2 INTRC Oscillator T1OSI 8 MHz T1OSO Oscillator ...
Page 14
... Clock Monitor Timer1 Timer2 Timer3 Timer4 CCP4 CCP5 EUSART1 EUSART2 Preliminary PORTA (1) RA0:RA7 PORTB (1) RB0:RB7 4 PORTC Access Bank (1) RC0:RC7 12 PORTD (1) RD0:RD7 PORTE (1) RE0:RE7 8 PORTF PRODL (1) RF0:RF7 8 PORTG 8 8 (1) RG0:RG5 8 PORTH 8 (1) RH0:RH7 PORTJ (1) RJ0:RJ7 Comparators MSSP1 MSSP2 2004 Microchip Technology Inc. ...
Page 15
... TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP RG5/MCLR RG5 MCLR V PP OSC1/CLKI/RA7 39 OSC1 CLKI RA7 OSC2/CLKO/RA6 40 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. ...
Page 16
... PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RA0/AN0 24 RA0 AN0 RA1/AN1 23 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 28 RA4 T0CKI RA5/AN4/HLVDIN 27 RA5 AN4 HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ...
Page 17
... TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0/FLT0 48 RB0 INT0 FLT0 RB1/INT1 47 RB1 INT1 RB2/INT2 46 RB2 INT2 RB3/INT3 45 RB3 INT3 RB4/KBI0 44 RB4 KBI0 RB5/KBI1/PGM 43 RB5 KBI1 PGM RB6/KBI2/PGC 42 RB6 KBI2 PGC RB7/KBI3/PGD 37 RB7 KBI3 PGD Legend: TTL = TTL compatible input ...
Page 18
... PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RC0/T1OSO/T13CKI 30 RC0 T1OSO T13CKI RC1/T1OSI/ECCP2/P2A 29 RC1 T1OSI (1) ECCP2 (1) P2A RC2/ECCP1/P1A 33 RC2 ECCP1 P1A RC3/SCK1/SCL1 34 RC3 SCK1 SCL1 RC4/SDI1/SDA1 35 RC4 SDI1 SDA1 RC5/SDO1 36 RC5 SDO1 RC6/TX1/CK1 31 RC6 TX1 ...
Page 19
... TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/PSP0 58 RD0 PSP0 RD1/PSP1 55 RD1 PSP1 RD2/PSP2 54 RD2 PSP2 RD3/PSP3 53 RD3 PSP3 RD4/PSP4/SDO2 52 RD4 PSP4 SDO2 RD5/PSP5/SDI2/SDA2 51 RD5 PSP5 SDI2 SDA2 RD6/PSP6/SCK2/SCL2 50 RD6 PSP6 SCK2 SCL2 RD7/PSP7/SS2 49 RD7 PSP7 ...
Page 20
... PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RE0/RD/P2D 2 RE0 RD P2D RE1/WR/P2C 1 RE1 WR P2C RE2/CS/P2B 64 RE2 CS P2B RE3/P3C 63 RE3 P3C RE4/P3B 62 RE4 P3B RE5/P1C 61 RE5 P1C RE6/P1B 60 RE6 P1B RE7/ECCP2/P2A 59 RE7 (2) ECCP2 (2) P2A Legend: TTL = TTL compatible input ...
Page 21
... TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF0/AN5 18 RF0 AN5 RF1/AN6/C2OUT 17 RF1 AN6 C2OUT RF2/AN7/C1OUT 16 RF2 AN7 C1OUT RF3/AN8 15 RF3 AN8 RF4/AN9 14 RF4 AN9 RF5/AN10/CV 13 REF RF5 AN10 CV REF RF6/AN11 12 RF6 AN11 RF7/SS1 11 RF7 SS1 Legend: TTL = TTL compatible input ...
Page 22
... PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RG0/ECCP3/P3A 3 RG0 ECCP3 P3A RG1/TX2/CK2 4 RG1 TX2 CK2 RG2/RX2/DT2 5 RG2 RX2 DT2 RG3/CCP4/P3D 6 RG3 CCP4 P3D RG4/CCP5/P1D 8 RG4 CCP5 P1D RG5 V 9, 25, 41 10, 26, 38 Legend: TTL = TTL compatible input ...
Page 23
... Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type Master Clear (input) or programming voltage (input). ...
Page 24
... TTL Digital I/O. I Analog Analog input 4. I Analog High/Low-Voltage Detect input. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output 2 I C™/SMB = I Preliminary Description 2 C/SMBus input buffer 2004 Microchip Technology Inc. ...
Page 25
... Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
Page 26
... EUSART1 synchronous clock (see related RX1/DT1). I/O ST Digital I/ EUSART1 asynchronous receive. I/O ST EUSART1 synchronous data (see related TX1/CK1). CMOS = CMOS compatible input or output Analog = Analog input O = Output 2 I C™/SMB = I Preliminary Description 2 C™ mode. 2 C/SMBus input buffer 2004 Microchip Technology Inc. ...
Page 27
... Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. ...
Page 28
... I/O ST Digital I/O. I/O TTL External memory address/data 15. I/O ST Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. O — ECCP2 PWM output A. CMOS = CMOS compatible input or output Analog = Analog input O = Output 2 I C™/SMB = I Preliminary Description 2 C/SMBus input buffer 2004 Microchip Technology Inc. ...
Page 29
... Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. ...
Page 30
... ECCP3 PWM output D. I/O ST Digital I/O. I/O ST Capture 5 input/Compare 5 output/PWM 5 output. O — ECCP1 PWM output D. See RG5/MCLR/V PP CMOS = CMOS compatible input or output Analog = Analog input O = Output 2 I C™/SMB = I Preliminary Description pin. 2 C/SMBus input buffer 2004 Microchip Technology Inc. ...
Page 31
... Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Buffer Type Type PORTH is a bidirectional I/O port. ...
Page 32
... Positive supply for logic and I/O pins. P — Ground reference for analog modules. P — Positive supply for analog modules. CMOS = CMOS compatible input or output Analog = Analog input O = Output 2 I C™/SMB = I Preliminary Description 2 C/SMBus input buffer 2004 Microchip Technology Inc. ...
Page 33
... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
Page 34
... Clock from Ext. System Preliminary EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) Open OSC2 EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX OSC2/CLKO /4 OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX I/O (OSC2) RA6 2004 Microchip Technology Inc. ...
Page 35
... Recommended values: 3 kΩ ≤ R ≤ 100 kΩ EXT 20 pF ≤ C ≤ 300 pF EXT 2004 Microchip Technology Inc. PIC18F8722 FAMILY 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
Page 36
... Locked Loop (PLL) in internal oscillator modes (see Figure 2-10). FIGURE 2-10: /4, OSC (OSCTUNE<6>) INTOSC CLKO OSC2 RA6 Preliminary by writing to TUN4:TUN0 in the OSCTUNE register INTOSC AND PLL BLOCK DIAGRAM MHz PLLEN Phase F IN Comparator F OUT Loop Filter ÷4 VCO SYSCLK 2004 Microchip Technology Inc. ...
Page 37
... Center frequency. Oscillator module is running at the calibrated frequency. 11111 • • 10000 = Minimum frequency Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY 2.6.5 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift affect the controller operation in a variety of ways ...
Page 38
... To compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow. To compensate, increment the OSCTUNE register. Preliminary 2004 Microchip Technology Inc. ...
Page 39
... WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F8722 family of devices are shown in Figure 2-11. See Section 25.0 “Special Features of the CPU” for Configuration register details. PIC18F6527/6622/6627/6722/8527/8622/8627/8722 HSPLL, INTOSC/PLL 4 x PLL OSCTUNE<6> OSCCON<6:4> ...
Page 40
... This formula assumes register that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power-Managed Modes”. Preliminary 2004 Microchip Technology Inc. ...
Page 41
... Modifying the SCSI:SCSO bits will cause an immediate clock source switch. 5: Modifying the IRCF3:IRCF0 bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY (1) R/W-0 R/W-0 R ...
Page 42
... EC INTIO modes are used as the primary clock source. are listed in OSC1 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level Preliminary (parameter 38, CSD OSC2 Pin 2004 Microchip Technology Inc. ...
Page 43
... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
Page 44
... When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Preliminary 2004 Microchip Technology Inc. ...
Page 45
... PRI_RUN RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. 2004 Microchip Technology Inc. PIC18F8722 FAMILY n-1 ...
Page 46
... The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n (1) Clock Transition OSC (1) (1) OST T PLL 1 2 n-1 n Clock (2) Transition PC OSTS bit Set . OSC Preliminary 2004 Microchip Technology Inc. ...
Page 47
... (approx). These intervals are not shown to scale. OST OSC PLL 2004 Microchip Technology Inc. PIC18F8722 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
Page 48
... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD PC Preliminary 2004 Microchip Technology Inc. ...
Page 49
... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. 2004 Microchip Technology Inc. PIC18F8722 FAMILY On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON< ...
Page 50
... None LP, XT OST HSPLL T OST CSD (1) EC (2) IOBST (4) INTOSC PLL (parameter 39, Table 28-12), the INTOSC stabilization period. IOBST Preliminary Clock Ready Status Bit (OSCCON) OSTS (1) IOFS (3) ( OSTS rc IOFS (4) ( OSTS rc IOFS (3) ( OSTS rc IOFS is the PLL Lock-out Timer 2004 Microchip Technology Inc. ...
Page 51
... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. 2004 Microchip Technology Inc. PIC18F8722 FAMILY A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1 ...
Page 52
... POR was set to ‘1’ by software immediately after POR). DS39646B-page 50 (1) U-0 R/W-1 R-1 — (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary (2) R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 53
... The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 4- ...
Page 54
... BOR Operation BOR disabled; must be enabled by reprogramming the configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the configuration bits. Preliminary 2004 Microchip Technology Inc. ...
Page 55
... T INTIO1, INTIO2 T Note 1: See parameter 33, Table 28-12 the nominal time required for the PLL to lock. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...
Page 56
... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39646B-page 54 T PWRT T OST T PWRT T OST T PWRT T OST Preliminary 2004 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
Page 57
... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ the nominal time required for the PLL to lock. T PLL 2004 Microchip Technology Inc. PIC18F8722 FAMILY , V RISE > PWRT T PWRT T OST T PWRT T OST T ...
Page 58
... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( Preliminary STKPTR Register POR BOR STKFUL STKUNF 2004 Microchip Technology Inc. ...
Page 59
... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F8722 FAMILY MCLR Resets, Power-on Reset, ...
Page 60
... Microchip Technology Inc. ...
Page 61
... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F8722 FAMILY MCLR Resets, Power-on Reset, ...
Page 62
... Microchip Technology Inc. ...
Page 63
... See Table 4-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 2004 Microchip Technology Inc. PIC18F8722 FAMILY MCLR Resets, Power-on Reset, ...
Page 64
... PIC18F8722 FAMILY NOTES: DS39646B-page 62 Preliminary 2004 Microchip Technology Inc. ...
Page 65
... NOP instruction). The PIC18F6527 and PIC18F8527 each have 48 Kbytes of Flash memory and can store up to 24,576 single-word instructions. The PIC18F6622 and PIC18F8622 each have 64 Kbytes of Flash memory and can store up to 32,768 single-word instructions ...
Page 66
... From No Access Yes Yes Yes Yes Yes Yes No Access Yes Yes Yes Preliminary 21 0000h 0008h 0018h On-Chip PIC18FX722 01FFFFh 1FFFFFh External Program Memory Table Read Table Write To From Yes Yes Yes Yes No Access No Access Yes Yes 2004 Microchip Technology Inc. ...
Page 67
... PIC18F6527 and PIC18F8527. 2: PIC18F6622 and PIC18F8622. 3: PIC18F6627 and PIC18F8627. 4: PIC18F6722 and PIC18F8722. 5: This is the only mode available on PIC18F6527/6622/6627/6722 devices. 6: Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Microprocessor Microcontroller with Boot Block Mode Mode ...
Page 68
... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Preliminary Stack Pointer STKPTR<4:0> 00010 2004 Microchip Technology Inc. ...
Page 69
... Note 1: Bit 7 and bit 6 are cleared by user software POR. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY When the stack has been popped enough times to unload the stack, the next POP will return a value of zero to the PC and set the STKUNF bit, while the Stack Pointer remains at zero ...
Page 70
... PCLATH and PCLATU registers. A read operation on PCL must be performed to update PCLATH and PCLATU. Preliminary FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK PCL PCL” instruction does not 2004 Microchip Technology Inc. ...
Page 71
... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 2004 Microchip Technology Inc. PIC18F8722 FAMILY on every Q1; the instruction is fetched from the program memory and latched into the instruction register during Q4 ...
Page 72
... LSB = 1 LSB = 0 → 0Fh 55h 055h EFh 03h 0006h F0h 00h C1h 23h 123h, 456h F4h 56h Preliminary 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h 2004 Microchip Technology Inc. ...
Page 73
... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF 2004 Microchip Technology Inc. PIC18F8722 FAMILY the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a condi- tional instruction that changes the PC ...
Page 74
... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. Preliminary 2004 Microchip Technology Inc. ...
Page 75
... Bank 12 FFh = 1101 00h Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh 2004 Microchip Technology Inc. PIC18F8722 FAMILY Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR ...
Page 76
... This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Preliminary (2) From Opcode 2004 Microchip Technology Inc. ...
Page 77
... Unimplemented registers are read as ‘0’. 3: This register is not available on 64-pin devices. 2004 Microchip Technology Inc. PIC18F8722 FAMILY The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions ...
Page 78
... N/A 58, 82 N/A 58, 82 N/A 58, 82 N/A 58, 82 N/A 58, 82 58, 82 ---- 0000 58, 82 xxxx xxxx ’ . Reset values are shown for 80-pin devices; 0 ‘ ’ . See Section 2.6.4 “PLL in 0 2004 Microchip Technology Inc. ‘ ’ ...
Page 79
... RG5 and LATG5 are only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 and LATG5 read as 6: Bit 7 and Bit 6 are cleared by user software POR. 7: Bit 21 of TBLPTRU allows access to the device configuration bits. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Bit 4 Bit 3 Bit 2 — ...
Page 80
... LATD0 60, 143 xxxx xxxx LATC1 LATC0 60, 140 xxxx xxxx LATB1 LATB0 60, 137 xxxx xxxx LATA1 LATA0 60, 135 xxxx xxxx ’ . Reset values are shown for 80-pin devices; 0 ‘ ’ . See Section 2.6.4 “PLL in 0 2004 Microchip Technology Inc. ‘ ’ ...
Page 81
... RG5 and LATG5 are only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 and LATG5 read as 6: Bit 7 and Bit 6 are cleared by user software POR. 7: Bit 21 of TBLPTRU allows access to the device configuration bits. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Bit 4 Bit 3 Bit 2 ...
Page 82
... The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. U-0 U-0 R/W-x R/W-x — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-x R/W-x R/W bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 83
... Purpose Register File” location in the Access Bank (Section 5.3.2 “Access Bank”) as the data source for the instruction. 2004 Microchip Technology Inc. PIC18F8722 FAMILY The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 5.3.1 “ ...
Page 84
... FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g OV, etc.). ADDWF, INDF1, 1 FSR1H:FSR1L Preliminary 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 F00h Bank 15 FFFh Data Memory 2004 Microchip Technology Inc. ...
Page 85
... Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET ...
Page 86
... Bank 15 F80h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 080h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F80h SFRs FFFh Data Memory Preliminary 2004 Microchip Technology Inc. 00h 60h 80h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
Page 87
... F80h by using the BSR. FFFh 2004 Microchip Technology Inc. PIC18F8722 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before ...
Page 88
... PIC18F8722 FAMILY NOTES: DS39646B-page 86 Preliminary 2004 Microchip Technology Inc. ...
Page 89
... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 90
... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. When set, Preliminary Table Latch (8-bit) TABLAT 2004 Microchip Technology Inc. ...
Page 91
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Legend Readable bit S = Bit can be set by software, but not cleared -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY U-0 R/W-0 R/W-x R/W-0 — ...
Page 92
... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TBLPTR<21:6> TABLE READ – TBLPTR<21:0> Preliminary TBLPTRL 0 TABLE WRITE TBLPTR<5:0> 2004 Microchip Technology Inc. ...
Page 93
... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD 2004 Microchip Technology Inc. PIC18F8722 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 94
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary 2004 Microchip Technology Inc. ...
Page 95
... EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. 2004 Microchip Technology Inc. PIC18F8722 FAMILY The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle ...
Page 96
... TBLWT holding register. ; loop until buffers are full Preliminary 2004 Microchip Technology Inc. ...
Page 97
... CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of TBLPTRU allows access to the device configuration bits. 2004 Microchip Technology Inc. PIC18F8722 FAMILY ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
Page 98
... PIC18F8722 FAMILY NOTES: DS39646B-page 96 Preliminary 2004 Microchip Technology Inc. ...
Page 99
... EXTERNAL MEMORY BUS Note: The external memory bus is not imple- mented on PIC18F6527/6622/6627/6722 (64-pin) devices. The External Memory Bus allows the device to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. It supports both 8-bit and 16-bit Data Width modes and four address widths from bits ...
Page 100
... Data Width mode is selected. U-0 R/W-0 R/W-0 U-0 — WAIT1 WAIT0 — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary U-0 R/W-0 R/W-0 — WM1 WM0 bit0 x = Bit is unknown 2004 Microchip Technology Inc. ...
Page 101
... Microchip Technology Inc. PIC18F8722 FAMILY 7.2.1 21-BIT ADDRESSING As an extension of 20-bit address width operation, the external memory bus can also fully address a 2 Mbyte memory space. This is done by using the Bus Address bit 0 (BA0) control line as the Least Significant bit of the address ...
Page 102
... BA0 for the byte address line and one I/O line to select between Byte and Word mode. The other 16-bit modes do not need BA0. JEDEC standard static RAM memories will use the signals for byte selection. Preliminary 2004 Microchip Technology Inc. the MEMCON register ...
Page 103
... Upper-order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. 2004 Microchip Technology Inc. PIC18F8722 FAMILY During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD15:AD0 bus ...
Page 104
... A<20:1> 373 D<15:0> 373 Preliminary cycle to an odd address JEDEC Word A<x:0> EPROM Memory D<15:0> ( Address Bus Data Bus Control Lines 2004 Microchip Technology Inc. ...
Page 105
... Upper-order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 106
... CF33h Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 2 Preliminary WAIT STATE 0Ch 9256h ‘1’ ‘1’ ‘0’ Wait 9256h Opcode Fetch ADDLW 55h from 000104h MOVLW 2004 Microchip Technology Inc. ...
Page 107
... CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction INST(PC – 2) Execution Note 1: Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h ...
Page 108
... This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. The appropriate level of BA0 control line is strobed on the LSb of the TBLPTR. D<7:0> A<19:0> 373 D<15:8> Address Bus Data Bus Control Lines Preliminary 2004 Microchip Technology Inc. A<x:1> A0 D<7:0> ...
Page 109
... AD<7:0> CE ALE OE Opcode Fetch Memory Cycle TBLRD * from 000100h Instruction INST(PC – 2) Execution Note 1: The address lines actually used depends on the address width selected. This example assumes 20-bit addressing. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 03Ah CCFh ABh 55h 0Eh ...
Page 110
... Note 1: The address lines actually used depends on the address width selected. This example assumes 16-bit addressing. DS39646B-page 108 00h 3Ah ABh 0Eh 55h Sleep Mode, Opcode Fetch MOVLW 55h from 007556h SLEEP 03Ah 0Eh 55h Opcode Fetch MOVLW 55h from 007556h Preliminary (2) Bus Inactive Q4 55h ‘1’ 2004 Microchip Technology Inc. ...
Page 111
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the external memory bus. Note 1: This register is not implemented on 64-pin devices. 2: Unimplemented in PIC18F6527/6622/6627/6722 devices. 2004 Microchip Technology Inc. PIC18F8722 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are sus- pended ...
Page 112
... PIC18F8722 FAMILY NOTES: DS39646B-page 110 Preliminary 2004 Microchip Technology Inc. ...
Page 113
... EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. 2004 Microchip Technology Inc. PIC18F8722 FAMILY The EECON1 register (Register 8-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
Page 114
... Legend Readable bit -n = Value at POR DS39646B-page 112 U-0 R/W-0 R/W-x R/W-0 — FREE WRERR WREN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary 2004 Microchip Technology Inc. R/S-0 R/S bit Bit is unknown ...
Page 115
... EECON1, WR BSF INTCON, GIE BCF EECON1, WREN 2004 Microchip Technology Inc. PIC18F8722 FAMILY Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
Page 116
... Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Increment the high address ; Not zero again ; Disable writes ; Enable interrupts Preliminary information (e.g., program 2004 Microchip Technology Inc. ...
Page 117
... CFGS IPR2 OSCFIP CMIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — — — ...
Page 118
... PIC18F8722 FAMILY NOTES: DS39646B-page 116 Preliminary 2004 Microchip Technology Inc. ...
Page 119
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2004 Microchip Technology Inc. PIC18F8722 FAMILY EXAMPLE 9- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
Page 120
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H 2004 Microchip Technology Inc. ...
Page 121
... Individual interrupts can be disabled through their corresponding enable bits. 2004 Microchip Technology Inc. PIC18F8722 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 122
... GIEL/PEIE IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Preliminary 2004 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEH/GIE GIEL/PEIE ...
Page 123
... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
Page 124
... DS39646B-page 122 R/W-1 R/W-1 R/W-1 INTEDG1 INTEDG2 INTEDG3 TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 125
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2004 Microchip Technology Inc. PIC18F8722 FAMILY R/W-0 R/W-0 ...
Page 126
... R-0 R/W-0 R/W-0 RC1IF TX1IF SSP1IF CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary Enable bit, GIE should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 127
... No TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY U-0 R/W-0 R/W-0 R/W-0 — EEIF BCL1IF ...
Page 128
... DS39646B-page 126 R-0 R-0 R/W-0 R/W-0 RC2IF TX2IF TMR4IF CCP5IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CCP4IF CCP3IF bit 0 2 C™ master was x = Bit is unknown 2004 Microchip Technology Inc. ...
Page 129
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY R/W-0 R/W-0 R/W-0 ADIE RC1IE TX1IE ...
Page 130
... R = Readable bit -n = Value at POR DS39646B-page 128 U-0 R/W-0 R/W-0 R/W-0 — EEIE BCL1IE HLVDIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary 2004 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown ...
Page 131
... CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY R-0 R-0 R/W-0 R/W-0 RC2IE TX2IE TMR4IE CCP5IE W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 132
... R = Readable bit -n = Value at POR DS39646B-page 130 R/W-1 R/W-1 R/W-1 R/W-1 RC1IP TX1IP SSP1IP CCP1IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 133
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY U-0 R/W-1 R/W-1 R/W-1 — EEIP BCL1IP HLVDIP W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 134
... R = Readable bit -n = Value at POR DS39646B-page 132 R/W-1 R/W-1 R/W-1 R/W-1 RC2IP TX2IP TMR4IP CCP5IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 CCP4IP CCP3IP bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 135
... POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY U-0 R/W-1 R-1 R-1 — RI ...
Page 136
... Example 10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary 2004 Microchip Technology Inc. ...
Page 137
... Port Note 1: I/O pins have diode protection to V 2004 Microchip Technology Inc. PIC18F8722 FAMILY 11.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 138
... RA5 RA4 RA3 RA2 LATA5 LATA4 LATA3 LATA2 TRISA5 TRISA4 TRISA3 TRISA2 VCFG1 VCFG0 PCFG3 PCFG2 Preliminary Description /4) in all oscillator modes except RC, Reset Bit 1 Bit 0 Values on page RA1 RA0 61 LATA1 LATA0 60 TRISA1 TRISA0 60 PCFG1 PCFG0 59 2004 Microchip Technology Inc. ...
Page 139
... RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Four of the PORTB pins (RB7:RB4) have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i ...
Page 140
... TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. I TTL Interrupt-on-pin change. O DIG Serial execution data output for ICSP and ICD operation I ST Serial execution data input for ICSP and ICD operation Preliminary Description (2) . (2) . (2) . 2004 Microchip Technology Inc. ...
Page 141
... TRISB TRISB7 TRISB6 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP Legend: Shaded cells are not used by PORTB. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 LATB5 LATB4 ...
Page 142
... CLRF PORTC CLRF LATC MOVLW 0CFh peripheral MOVWF TRISC Preliminary INITIALIZING PORTC ; Initialize PORTC by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs 2004 Microchip Technology Inc. ...
Page 143
... I C/SMB = I C/SMBus input buffer Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2 when CCP2MX configuration bit is set. 2004 Microchip Technology Inc. PIC18F8722 FAMILY I/O I/O Type O DIG LATC< ...
Page 144
... Synchronous serial data input (EUSART1 module). User must configure as an input. Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATC4 LATC3 LATC2 TRISC5 TRISC4 TRISC3 TRISC2 Preliminary Description Reset Bit 1 Bit 0 Values on page RC1 RC0 60 LATC1 LATC0 60 TRISC1 TRISC0 60 2004 Microchip Technology Inc. ...
Page 145
... When the interface is enabled, PORTD is the low-order byte of the multiplexed address/data bus (AD7:AD0). The TRISD bits are also overridden. 2004 Microchip Technology Inc. PIC18F8722 FAMILY PORTD can also be configured to function as an 8-bit wide parallel microprocessor port by setting the PSPMODE control bit (PSPCON<4>). In this mode, parallel port data takes priority over other digital I/O (but not the external memory interface) ...
Page 146
... External memory interface, data bit 4 input. O DIG PSP read data output (LATD<4>). Takes priority over port and PSP data. I TTL PSP write data input. O DIG SPI™ data output (MSSP2 module). Takes priority over PSP and port data. Preliminary Description 2004 Microchip Technology Inc. ...
Page 147
... SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name Bit 7 Bit 6 PORTD RD7 RD6 LATD LATD7 LATD6 TRISD TRISD7 TRISD6 2004 Microchip Technology Inc. PIC18F8722 FAMILY I/O I/O Type O DIG LATD<5> data output PORTD<5> data input. O DIG External memory interface, address/data bit 5 output. Takes priority over PSP, MSSP and port data ...
Page 148
... EXAMPLE 11-5: INITIALIZING PORTE CLRF PORTE ; Initialize PORTE by ; clearing output ; data latches CLRF LATE ; Alternate method ; to clear output ; data latches MOVLW 03h ; Value used to ; initialize data ; direction MOVWF TRISE ; Set RE<1:0> as inputs ; RE<7:2> as outputs Preliminary 2004 Microchip Technology Inc. pins (RE0/AD8/RD/P2D, ...
Page 149
... TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Alternate assignment for ECCP2 when CCP2MX configuration bit is cleared (all devices in Microcontroller mode). 2: Implemented on 80-pin devices only. 2004 Microchip Technology Inc. PIC18F8722 FAMILY I/O I/O Type ...
Page 150
... May be configured for tri-state during Enhanced PWM shutdown events. Bit 5 Bit 4 Bit 3 Bit 2 RE5 RE4 RE3 RE2 LATE5 LATE4 LATE3 LATE2 TRISE5 TRISE4 TRISE3 TRISE2 Preliminary Description Reset Bit 1 Bit 0 Values on page RE1 RE0 60 LATE1 LATE0 60 TRISE1 TRISE0 60 2004 Microchip Technology Inc. ...
Page 151
... RF2 may be used as comparator inputs or outputs by setting the appropriate bits in the CMCON register. To use RF0:RF6 as digital inputs necessary to turn off the A/D inputs. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Note Power-on Reset, the RF6:RF0 pins are configured as analog inputs and read as ‘ ...
Page 152
... TRISF4 TRISF3 TRISF2 RF5 RF4 RF3 RF2 LATF5 LATF4 LATF3 LATF2 VCFG1 VCFG0 PCFG3 PCFG2 C2INV C1INV CIS CM2 Preliminary Description Reset Bit 1 Bit 0 Values on page TRISF1 TRISF0 60 RF1 RF0 60 LATF1 LATF0 60 PCFG1 PCFG0 59 CM1 CM0 59 2004 Microchip Technology Inc. ...
Page 153
... The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. 2004 Microchip Technology Inc. PIC18F8722 FAMILY The sixth pin of PORTG (RG5/MCLR/V only pin. Its operation is controlled by the MCLRE configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...
Page 154
... PORTG<5> data input; enabled when MCLRE configuration bit is clear External Master Clear input; enabled when MCLRE configuration bit is set. I ANA High-voltage detection; used for ICSP™ mode entry detection. Always available regardless of pin mode. Preliminary Description 2004 Microchip Technology Inc. ...
Page 155
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: RG5 and LATG5 are only available when MCLR is disabled (MCLRE configuration bit = 0; otherwise, RG5 and LATG5 read as ‘0’. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Bit 5 Bit 4 ...
Page 156
... EXAMPLE 11-8: CLRF PORTH CLRF LATH MOVLW 0CFh MOVWF TRISH Preliminary INITIALIZING PORTH ; Initialize PORTH by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RH3:RH0 as inputs ; RH5:RH4 as outputs ; RH7:RH6 as inputs 2004 Microchip Technology Inc. ...
Page 157
... TRISH TRISH7 TRISH6 PORTH RH7 RH6 LATH LATH7 LATH6 ADCON1 — — 2004 Microchip Technology Inc. PIC18F8722 FAMILY I/O Type DIG LATH<0> data output PORTH<0> data input. DIG External memory interface, address line 16. Takes priority over port data. DIG LATH<1> data output. ...
Page 158
... EXAMPLE 11-9: CLRF PORTJ CLRF LATJ MOVLW 0xCF MOVWF TRISJ Preliminary INITIALIZING PORTJ ; Initialize PORTJ by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs 2004 Microchip Technology Inc. ...
Page 159
... TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Name Bit 7 Bit 6 PORTJ RJ7 RJ6 LATJ LATJ7 LATJ6 TRISJ TRISJ7 TRISJ6 2004 Microchip Technology Inc. PIC18F8722 FAMILY I/O I/O Type O DIG LATJ<0> data output PORTJ<0> data input. O DIG External memory interface address latch enable control output. Takes priority over digital I/O ...
Page 160
... CKx or PORTD Data Latch PORTD EN EN TRIS Latch RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pin has protection diodes to V Preliminary 2004 Microchip Technology Inc. RDx pin TTL Read RD TTL Chip Select CS TTL Write TTL WR and ...
Page 161
... PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — ...
Page 162
... TX1IE SSP1IE CCP1IE RC1IP TX1IP SSP1IP CCP1IP Preliminary Reset Bit 1 Bit 0 Values on page RD1 RD0 60 LATD1 LATD0 60 TRISD1 TRISD0 60 RE1 RE0 60 LATE1 LATE0 60 TRISE1 TRISE0 60 — — — 59 INT0IF RBIF 57 TMR2IF TMR1IF 60 TMR2IE TMR1IE 60 TMR2IP TMR1IP 60 2004 Microchip Technology Inc. ...
Page 163
... Prescale value Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1 ...
Page 164
... Sync with Internal TMR0L Clocks Delay Preliminary ). There is a delay between OSC Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus 2004 Microchip Technology Inc. ...
Page 165
... Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
Page 166
... PIC18F8722 FAMILY NOTES: DS39646B-page 164 Preliminary 2004 Microchip Technology Inc. ...
Page 167
... Enables Timer1 0 = Stops Timer1 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 168
... Preliminary 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus 2004 Microchip Technology Inc. ...
Page 169
... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 13-1 for additional information about capacitor selection. 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 170
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary 2004 Microchip Technology Inc. ...
Page 171
... Timer1 Register High Byte T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. 2004 Microchip Technology Inc. PIC18F8722 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 172
... PIC18F8722 FAMILY NOTES: DS39646B-page 170 Preliminary 2004 Microchip Technology Inc. ...
Page 173
... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options ...
Page 174
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TX1IF SSP1IF CCP1IF TX1IE SSP1IE CCP1IE TX1IP SSP1IP CCP1IP Preliminary Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 57 TMR2IF TMR1IF 60 TMR2IE TMR1IE 60 TMR2IP TMR1IP 2004 Microchip Technology Inc. ...
Page 175
... Enables Timer3 0 = Stops Timer3 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 15-2. The Timer3 module is controlled through the T3CON register (Register 15-1) ...
Page 176
... Clear TMR3 TMR3L 8 Preliminary 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR3H 8 8 Internal Data Bus 2004 Microchip Technology Inc. ...
Page 177
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 15.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
Page 178
... PIC18F8722 FAMILY NOTES: DS39646B-page 176 Preliminary 2004 Microchip Technology Inc. ...
Page 179
... Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY 16.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP modules. The TMR4 register is readable and writable and is cleared on any device Reset ...
Page 180
... INT0IE RBIE TMR0IF TX2IP TMR4IP CCP5IP RC2IF TX2IF TMR4IF CCP5IF TX2IE TMR4IE CCP5IE Preliminary Sets Flag bit TMR4IF (1) Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 57 CCP4IP CCP3IP 60 CCP4IF CCP3IF 60 CCP4IE CCP3IE 60 61 T4CKPS1 T4CKPS0 61 61 2004 Microchip Technology Inc. ...
Page 181
... Section 17.3.4 “Special Event Trigger” for effects of the trigger) 11xx = PWM mode Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY Capture and Compare operations described in this chap- ter apply to all standard and Enhanced CCP modules. The operations of PWM mode described in Section 17.4 “ ...
Page 182
... Timer3 is used for all Capture and Compare operations for all CCP modules. Timer4 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. Timer1 and Timer2 are not available. 2004 Microchip Technology Inc. ...
Page 183
... RG3/CCP4 pin and Edge Detect CCP1CON<3:0> Q’s 2004 Microchip Technology Inc. PIC18F8722 FAMILY 17.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false inter- rupts ...
Page 184
... The ECCP2 special event trigger can also start an A/D conversion. In order to do this, the A/D converter must already be enabled. Set Flag bit CCP4IF Output Logic Match T3CCP2 Mode Select TMR1H Preliminary Special Event Trigger mode CCPR4H CCPR4L Comparator 0 1 TMR1L TMR3H TMR3L 2004 Microchip Technology Inc. ...
Page 185
... P3M0 CCP4CON — — CCP5CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: Implemented on 80-pin devices only. 2004 Microchip Technology Inc. PIC18F8722 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
Page 186
... CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. Preliminary • OSC (TMR2 Prescale Value) “Timer2 Module” and L:CCP CON<5:4>) • • (TMR2 Prescale Value) OSC 2004 Microchip Technology Inc. ...
Page 187
... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) 2004 Microchip Technology Inc. PIC18F8722 FAMILY 17.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. ...
Page 188
... DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 Preliminary Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 57 PD POR BOR 56 TMR2IF TMR1IF 60 TMR2IE TMR1IE 60 TMR2IP TMR1IP 60 CCP4IF CCP3IF 60 CCP4IE CCP3IE 60 CCP4IP CCP3IP 2004 Microchip Technology Inc. ...
Page 189
... PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F8722 FAMILY The control register for the Enhanced CCP modules is shown in Register 18-1. It differs from the CCPxCON registers discussed Compare/PWM (CCP) Modules” ...
Page 190
... The final option is that the ABW<1:0> configuration bits can be used to select 8, 12 20-bit EMB address- ing. Pins not assigned to EMB address pins are available for peripheral or port functions. Preliminary 2004 Microchip Technology Inc. devices, the ...
Page 191
... With ECCP1 in Quad PWM mode, the CCP5 module’s output overrides P1D. 2: The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function. 2004 Microchip Technology Inc. PIC18F8722 FAMILY RC2 RE6 RE5 PIC18F6527/6622/6627/6722 Devices: RE6 RE5 P1A P1B RE5 P1A P1B ...
Page 192
... PIC18F6527/6622/6627/6722 Devices, CCP2MX = 1: Compatible CCP RB3/INT3 00xx 11xx Dual PWM RB3/INT3 10xx 11xx Quad PWM RB3/INT3 x1xx 11xx PIC18F6527/6622/6627/6722 Devices CCP2MX = 0: Compatible CCP RB3/INT3 00xx 11xx Dual PWM RB3/INT3 10xx 11xx Quad PWM RB3/INT3 x1xx 11xx PIC18F8527/8622/8627/8722 Devices, CCP2MX = 1, Microcontroller mode: ...
Page 193
... With ECCP3 in Quad PWM mode, the CCP4 module’s output overrides P3D. 2: The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function. 2004 Microchip Technology Inc. PIC18F8722 FAMILY RG0 RE4 RE3 PIC18F6527/6622/6627/6722 Devices: RE4 RE3 P3A P3B RE3 P3A P3B ...
Page 194
... The Timer2 postscaler (see Section 14.0 “Timer2 Module”) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. Preliminary • OSC (TMR2 Prescale Value) 2004 Microchip Technology Inc. ...
Page 195
... In PWM mode, CCPR1H is a read-only register. TABLE 18-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) 2004 Microchip Technology Inc. PIC18F8722 FAMILY P1M1<1:0> CCP1M<3:0> ECCP1/P1A P1B Output R ...
Page 196
... Section 18.4 “Enhanced PWM Mode”. The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 18-2. 0 Duty Cycle Period (1) (1) Delay Delay Preliminary 2004 Microchip Technology Inc. PR2 + 1 ...
Page 197
... OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 “Programmable Dead-Band Delay”). 2004 Microchip Technology Inc. PIC18F8722 FAMILY 0 Duty Cycle Period (1) (1) Delay Delay ...
Page 198
... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- Preliminary HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver 2004 Microchip Technology Inc. ...
Page 199
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. 2004 Microchip Technology Inc. PIC18F8722 FAMILY P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data latches. Alternatively, P1B and P1C can be assigned to PORTH< ...
Page 200
... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. Preliminary QC FET Driver FET Driver QD 2004 Microchip Technology Inc. ...