PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet - Page 80

• Manufacturer Part Number: PIC18F6527-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6527-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F8722 FAMILY
TABLE 5-3:
DS39646C-page 78
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
EEADRH
EEADR
EEDATA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
MEMCON
OSCTUNE
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA
Legend:
Note
File Name
(2)
(2)
(2)
(2)
1:
2:
3:
4:
5:
6:
7:
(2)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, this bit reads as ‘0’.
These registers and/or bits are not implemented on 64-pin devices and are read as
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as
INTOSC Modes”.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 and LATG5 read as
Bit 7 and Bit 6 are cleared by user software or by a POR.
Bit 21 of TBLPTRU allows access to the device Configuration bits.
EUSART1 Baud Rate Generator Register Low Byte
EUSART1 Receive Register
EUSART1 Transmit Register
EEPROM Address Register Low Byte
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
TRISA7
LATA7
OSCFIP
OSCFIF
OSCFIE
INTSRC
EEPGD
SSP2IP
SSP2IF
SSP2IE
TRISH7
TRISF7
TRISE7
TRISD7
TRISC7
TRISB7
TRISJ7
PSPIP
PSPIE
EBDIS
LATH7
LATF7
LATE7
LATD7
LATC7
LATB7
CSRC
PSPIF
LATJ7
SPEN
Bit 7
IBF
—
—
—
REGISTER FILE SUMMARY (CONTINUED)
(4)
(4)
TRISA6
PLLEN
LATA6
BCL2IE
TRISH6
TRISE6
TRISD6
TRISC6
TRISB6
BCL2IP
BCL2IF
TRISJ6
TRISF6
LATH6
LATE6
LATD6
LATC6
LATB6
LATJ6
LATF6
CFGS
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
Bit 6
OBF
RX9
TX9
—
—
—
—
(4)
(3)
(4)
LATG5
TRISH5
TRISD5
TRISC5
TRISF5
TRISE5
TRISB5
TRISA5
TRISJ5
WAIT1
LATH5
LATE5
LATD5
LATC5
LATB5
RC2IP
RC2IF
RC2IE
RC1IP
RC1IF
RC1IE
LATJ5
LATF5
LATA5
TXEN
SREN
IBOV
Bit 5
—
—
—
—
—
—
—
(5)
PSPMODE
TRISH4
TRISG4
TRISD4
TRISC4
TRISF4
TRISE4
TRISB4
TRISA4
TRISJ4
WAIT0
LATH4
LATG4
LATD4
LATC4
CREN
LATF4
LATE4
LATB4
LATA4
SYNC
FREE
TX2IP
TX2IF
TX2IE
TX1IP
TX1IF
TX1IE
LATJ4
TUN4
Bit 4
EEIP
EEIF
EEIE
—
WRERR
TMR4IP
TMR4IF
TMR4IE
TRISH3
TRISG3
TRISD3
TRISC3
SENDB
ADDEN
BCL1IP
BCL1IF
BCL1IE
SSP1IP
SSP1IF
SSP1IE
TRISF3
TRISE3
TRISB3
TRISA3
TRISJ3
LATH3
LATG3
LATD3
LATC3
LATF3
LATE3
LATB3
LATA3
LATJ3
TUN3
Bit 3
—
—
—
CCP5IP
CCP5IF
CCP5IE
CCP1IP
CCP1IF
CCP1IE
TRISG2
HLVDIP
HLVDIF
HLVDIE
TRISH2
TRISF2
TRISE2
TRISD2
TRISC2
TRISB2
TRISA2
TRISJ2
LATG2
BRGH
WREN
LATH2
LATF2
LATE2
LATD2
LATC2
LATB2
LATA2
FERR
LATJ2
TUN2
Bit 2
—
—
—
‘
0
’
. Reset values are shown for 80-pin devices;
EEPROM Address
Register High Byte
CCP4IP
CCP4IE
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TRISG1
CCP4IF
TRISH1
TRISF1
TRISE1
TRISD1
TRISC1
TRISB1
TRISA1
TRISJ1
LATG1
LATH1
LATF1
LATE1
LATD1
LATC1
LATB1
LATA1
TRMT
OERR
LATJ1
TUN1
WM1
Bit 1
WR
—
© 2008 Microchip Technology Inc.
TMR1IP
TMR1IE
CCP3IP
CCP3IF
CCP3IE
CCP2IP
CCP2IF
CCP2IE
TMR1IF
TRISH0
TRISG0
TRISE0
TRISD0
TRISC0
TRISB0
TRISA0
TRISJ0
TRISF0
LATH0
LATG0
LATE0
LATD0
LATC0
LATB0
LATJ0
LATF0
LATA0
RX9D
TUN0
TX9D
‘
WM0
Bit 0
0
RD
—
’
. See Section 2.6.4 “PLL in
0000 ----
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
---- --00
0000 0000
0000 0000
0000 0000
xx-0 x000
1111 1111
0000 0000
0000 0000
11-1 1111
00-0 0000
00-0 0000
1111 1111
0000 0000
0000 0000
0-00 --00
00-0 0000
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
--xx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
POR, BOR
Value on
on page:
Details
59, 252
59, 252
59, 260
59, 257
59, 248
59, 249
60, 131
60, 125
60, 129
60, 131
60, 125
60, 128
60, 130
60, 124
60, 127
60, 157
60, 155
60, 153
60, 150
60, 148
60, 143
60, 140
60, 137
60, 135
60, 156
60, 154
60, 151
60, 149
60, 146
60, 143
60, 140
60, 137
60, 135
59, 111
59, 111
59, 111
59, 88
59, 89
60, 96
35, 60
‘
0
’
.