PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet - Page 138

• Manufacturer Part Number: PIC18F6527-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6527-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F8722 FAMILY
TABLE 11-1:
TABLE 11-2:
DS39646C-page 136
RA0/AN0
RA1/AN1
RA2/AN2/V
RA3/AN3/V
RA4/T0CKI
RA5/AN4/HLVDIN
OSC2/CLKO/RA6
Legend:
PORTA
LATA
TRISA
ADCON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
OSC1/CLKI/RA7
Pin Name
Name
REF
REF
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST= Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
-
+
TRISA7
LATA7
RA7
Function
Bit 7
PORTA FUNCTIONS
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
HLVDIN
V
T0CKI
—
OSC2
CLKO
OSC1
V
CLKI
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
RA4
RA5
AN4
RA6
RA7
REF
REF
(1)
(1)
(1)
+
-
TRISA6
LATA6
Setting
RA6
TRIS
Bit 6
0
1
1
0
1
1
0
1
1
1
0
1
1
1
0
1
x
0
1
1
1
x
x
0
1
x
x
0
1
—
(1)
(1)
(1)
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
TRISA5
VCFG1
LATA5
Bit 5
RA5
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
TTL
I/O
ST
ST
TRISA4
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
A/D input channel 0. Default input configuration on POR; does not affect
digital output.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
A/D input channel 1. Default input configuration on POR; does not affect
digital output.
LATA<2> data output; not affected by analog input.
PORTA<2> data input. Disabled when analog functions enabled.
A/D input channel 2. Default input configuration on POR.
Comparator voltage reference low input and A/D voltage reference low input.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3. Default input configuration on POR.
Comparator voltage reference high input and A/D voltage reference
high input.
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
Timer0 clock input.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D input channel 4. Default configuration on POR.
High/Low-Voltage Detect external trip point input.
Main oscillator feedback output connection (XT, HS, HSPLL and LP modes).
System cycle clock output (F
INTIO7 and EC.
LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only.
Main oscillator input connection.
Main clock input connection.
LATA<7> data output. Disabled in external oscillator modes.
PORTA<7> data input. Disabled in external oscillator modes.
VCFG0
LATA4
Bit 4
RA4
TRISA3
PCFG3
LATA3
Bit 3
RA3
TRISA2
PCFG2
LATA2
Bit 2
RA2
OSC
Description
/4) in all oscillator modes except RC,
TRISA1
PCFG1
LATA1
Bit 1
RA1
© 2008 Microchip Technology Inc.
TRISA0
PCFG0
LATA0
Bit 0
RA0
on page
Values
Reset
61
60
60
59