PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet - Page 269

• Manufacturer Part Number: PIC18F6527-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6527-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 20-8:
© 2008 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISC
TRISG
RCSTAx
RCREGx
TXSTAx
BAUDCONx
SPBRGHx
SPBRGx
Legend:
Name
— = unimplemented, read as ‘
EUSARTx Receive Register
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
ABDOVF
TRISC7
PSPIE
PSPIP
PSPIF
CSRC
SPEN
Bit 7
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
TRISC6
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
—
TMR0IE
TRISC5
RC1IE
RC1IP
RC1IF
SREN
TXEN
0
Bit 5
’. Shaded cells are not used for synchronous master reception.
—
—
TRISC4
TRISG4
INT0IE
CREN
TX1IF
TX1IE
TX1IP
SYNC
SCKP
Bit 4
SSP1IE
SSP1IP
TRISC3
TRISG3
ADDEN
SSP1IF
SENDB
BRG16
RBIE
Bit 3
PIC18F8722 FAMILY
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISC2
TRISG2
BRGH
FERR
Bit 2
—
TMR2IF
TMR2IE
TMR2IP
TRISG1
TRISC1
INT0IF
OERR
TRMT
WUE
Bit 1
TMR1IE
TMR1IP
TMR1IF
TRISC0
TRISG0
ABDEN
RX9D
TX9D
DS39646C-page 267
RBIF
Bit 0
on page
Values
Reset
57
60
60
60
60
60
59
59
59
61
61
59