PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet - Page 79

• Manufacturer Part Number: PIC18F6527-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6527-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 5-3:
© 2008 Microchip Technology Inc.
STATUS
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSP1BUF
SSP1ADD
SSP1STAT
SSP1CON1
SSP1CON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
CCPR3H
CCPR3L
CCP3CON
ECCP1AS
CVRCON
CMCON
TMR3H
TMR3L
T3CON
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, this bit reads as ‘0’.
These registers and/or bits are not implemented on 64-pin devices and are read as
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as
INTOSC Modes”.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 and LATG5 read as
Bit 7 and Bit 6 are cleared by user software or by a POR.
Bit 21 of TBLPTRU allows access to the device Configuration bits.
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Enhanced Capture/Compare/PWM Register 1 High Byte
Enhanced Capture/Compare/PWM Register 1 Low Byte
Enhanced Capture/Compare/PWM Register 2 High Byte
Enhanced Capture/Compare/PWM Register 2 Low Byte
Enhanced Capture/Compare/PWM Register 3 High Byte
Enhanced Capture/Compare/PWM Register 3 Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0
VDIRMAG
TMR0ON
CVREN
C2OUT
IDLEN
WCOL
GCEN
ADFM
RD16
P1M1
P2M1
P3M1
RD16
IPEN
SMP
Bit 7
—
—
—
—
—
REGISTER FILE SUMMARY (CONTINUED)
SBOREN
T2OUTPS3
ACKSTAT
T3CCP2
SSPOV
CVROE
T08BIT
T1RUN
C1OUT
IRCF2
P1M0
P2M0
P3M0
Bit 6
CKE
—
—
—
—
—
—
(1)
T2OUTPS2
2
T1CKPS1
T3CKPS1
C™ Slave mode. MSSP1 Baud Rate Reload Register in I
SSPEN
ACKDT
VCFG1
ACQT2
DC1B1
DC2B1
DC3B1
IRVST
C2INV
IRCF1
CVRR
CHS3
T0CS
Bit 5
D/A
—
—
—
T2OUTPS1
T1CKPS0
T3CKPS0
HLVDEN
ACKEN
VCFG0
ACQT1
CVRSS
DC1B0
DC2B0
DC3B0
IRCF0
C1INV
CHS2
T0SE
Bit 4
CKP
—
RI
N
P
T2OUTPS0
T1OSCEN
PSS1AC1
CCP1M3
CCP2M3
CCP3M3
HLVDL3
T3CCP1
SSPM3
PCFG3
ACQT0
RCEN
OSTS
CHS1
CVR3
Bit 3
PSA
CIS
OV
TO
—
S
PIC18F8722 FAMILY
PSS1AC0
TMR2ON
CCP1M2
CCP2M2
CCP3M2
T1SYNC
T3SYNC
HLVDL2
SSPM2
PCFG2
ADCS2
T0PS2
CHS0
CVR2
IOFS
Bit 2
PEN
CM2
R/W
PD
—
Z
‘
0
’
. Reset values are shown for 80-pin devices;
GO/DONE
T2CKPS1
PSS1BD1
TMR1CS
TMR3CS
CCP1M1
CCP2M1
CCP3M1
HLVDL1
SSPM1
2
PCFG1
ADCS1
T0PS1
RSEN
CVR1
SCS1
C Master mode.
Bit 1
POR
CM1
DC
UA
—
PSS1BD0
SWDTEN
T2CKPS0
TMR1ON
TMR3ON
CCP1M0
CCP2M0
CCP3M0
HLVDL0
SSPM0
PCFG0
ADCS0
T0PS0
ADON
SCS0
CVR0
‘
Bit 0
BOR
SEN
CM0
0
BF
C
’
. See Section 2.6.4 “PLL in
DS39646C-page 77
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0100 q000
0-00 0101
0q-1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
--00 0000
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
POR, BOR
--- ---0
Value on
on page:
58, 169,
58, 162,
58, 163,
58, 163
58, 163
58, 161
58, 291
58, 313
58, 133
58, 169
58, 169
58, 165
58, 172
58, 172
58, 171
58, 170
58, 173
59, 280
59, 280
59, 271
59, 272
59, 273
59, 180
59, 180
59, 187
59, 180
59, 180
59, 179
59, 180
59, 180
59, 179
59, 201
59, 287
59, 289
59, 175
59, 175
59, 173
Details
50, 56,
58, 80
39, 58
170
171
172
‘
0
’
.