ADSP-21367 Analog Devices, ADSP-21367 Datasheet

ADSP-21367

Manufacturer Part Number

ADSP-21367

Description

SHARC Processor

Manufacturer

Analog Devices

Datasheet

1.ADSP-21367.pdf (48 pages)

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Preliminary Technical Data

SUMMARY

High performance 32-bit/40-bit floating point processor

Audio decoder and post processor-algorithm support with

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

optimized for high performance automotive audio

processing

32-bit floating-point implementations

Non-volatile memory may be configured to support audio

decoders and post processor-algorithms like PCM, Dolby

Digital EX, Dolby Prologic IIx, Dolby Digital Plus, Dolby

headphone, DTS 96/24, Neo:6, DTS ES, DTS Lossless,

MPEG2 AAC, MPEG2 2channel, MP3, WMAPro, and Multi-

channel encoder. Functions like Bass management, Delay,

Speaker equalization, Graphic equalization, Decoder/post-

PROCESSING

EL EMENT

(PEX)

GPIO FLAGS/

8X4X32

IRQ/TIMEXP

DAG1

PWM (16)

PROCESSING

CORE PROCESSOR

ELEMENT

8X4X32

DAG2

(PEY)

SRC (8 CHANNELS)

PRECISION CLOCK

GENERATORS (4)

SPDIF (RX/TX)

PX REGISTER

TIMER

DIGITAL AUDIO INTERFACE

SEQUENCER

PROGRAM

Figure 1. Functional Block Diagram – Processor Core

INSTRUCTION

32 X 48-BIT

CACHE

SERIAL PORTS (8)

INPUT DATA PORT/

DAI PINS

PDAP

CONTROL, STATUS, & DATA BUFFERS

ADDR

IOP REGIST ER (MEMORY MAPPED)

2M BIT RAM, 6M BIT ROM

IOA(24)

ON-CHIP MEMORY

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel:781.329.4700

Fax:781.326.8703

Single-Instruction Multiple-Data (SIMD) computational

On-chip memory—2M bit of on-chip SRAM and a dedicated

Code compatible with all other members of the SHARC family

The ADSP-21367 is available with a 400 MHz core instruction

4 BLOCKS OF

processor algorithm combination support will vary

depending upon the chip version and the system configu-

rations. Please visit www.analog.com

architecture

6M bit of on-chip mask-programmable ROM

rate with unique audio centric peripherals such as the Digi-

tal Audio Interface, S/PDIF transceiver, serial ports, 8-

channel asynchronous sample rate converter, precision

clock generators and more. For complete ordering infor-

mation, see

DATA

Ordering Guide on page 47

IOD(32)

SPI PORT (2)

INTERFACE

TWO WIRE

DPI PINS

DIGITAL PERIPHERAL INTERFACE

SHARC

ASYNCHRONOUS

CONTROL LER

INTERFACE

MEMORY

SDRAM

CONTROLLER

EXTERNAL PORT

34 CHANNE LS

DMA

I/O PROCESSOR

ADSP-21367

JTAG TEST & EMULATION

Processor

www.analog.com

MEMORY DMA (2)

MEMORY-T O-

TIMERS (3)

UART (2)

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

C ONTROL

ADDRESS

DATA

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