ADSP-21367 Analog Devices, ADSP-21367 Datasheet - Page 9

• Manufacturer Part Number: ADSP-21367
• Description: SHARC Processor
• Manufacturer: Analog Devices

Preliminary Technical Data
Two Wire Interface Port (TWI)
The TWI is a bi-directional 2-wire, serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
The TWI Master incorporates the following features:
Pulse Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave-
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non
paired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
mid-point of the PWM period. In double update mode, a sec-
ond updating of the PWM registers is implemented at the mid-
point of the PWM period. In this mode, it is possible to produce
asymmetrical PWM patterns that produce lower harmonic dis-
tortion in three-phase PWM inverters.
ROM Based Security
The ADSP-21367 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
external code, executing exclusively from internal SRAM/ROM.
Additionally, the processor is not freely accessible via the JTAG
port. Instead, a unique 64-bit key, which must be scanned in
through the JTAG or Test Access Port will be assigned to each
customer. The device will ignore a wrong key. Emulation fea-
tures and external boot modes are only available after the
correct key is scanned.
• Simultaneous Master and Slave operation on multiple
• Digital filtering and timed event processing
• 7 and 10 bit addressing
• 100K bits/s and 400K bits/s data rates
• Low interrupt rate
device systems with support for multi master data
arbitration
Rev. PrA | Page 9 of 48 | November 2004
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues.
Program Booting
The internal memory of the ADSP-21367 boots at system
power-up from an 8-bit EPROM via the external port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1–0) pins (see
page
either a master or slave device, or it can immediately begin exe-
cuting from ROM.
Power Supplies
The ADSP-21367 has separate power supply connections for the
internal (V
power supplies. The internal and analog supplies must meet the
1.3V requirement. The external supply must meet the 3.3V
requirement. All external supply pins must be connected to the
same power supply.
Note that the analog supply (A
clock generator PLL. To produce a stable clock, programs
should provide an external circuit to filter the power input to
the A
an example circuit, see
a wide trace for the analog ground (A
decoupling capacitor as close as possible to the pin. Note that
the A
processor and not the analog ground plane on the board.
more information, see Electrical Characteristics on page 15.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21367 pro-
cessor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor's JTAG interface ensures that the
emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate “Emulator Hardware User's Guide”.
V
14). Selection of the boot source is controlled via the SPI as
VDD
VSS
DDINT
and A
pin. Place the filter as close as possible to the pin. For
DDINT
Figure 2. Analog Power (A
VDD
), external (V
pins specified in
Figure
10
0.1 F
DDEXT
2. To prevent noise coupling, use
VDD
) powers the ADSP-21367’s
VDD
), and analog (A
Figure 2
A
VSS
VSS
) Filter Circuit
) signal and install a
ADSP-21367
0.01 F
are inputs to the
VDD
Table 4 on
/A
A
For
VDD
VSS
)