ADSP-21367 Analog Devices, ADSP-21367 Datasheet - Page 31

• Manufacturer Part Number: ADSP-21367
• Description: SHARC Processor
• Manufacturer: Analog Devices

Preliminary Technical Data
Sample Rate Converter—Serial Input Port
The SRC input signals (SCLK, FS, and SDATA) are routed from
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided in
Table 25. SRC, Serial Input Port
1
Parameter
Timing Requirements
t
t
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SRCSFS
SRCHFS
SRCSD
SRCHD
SRCCLKW
SRCCLK
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
SData Hold After SCLK Rising Edge
Clock Width
Clock Period
Table 25
are valid at the DAI_P20–1 pins.
DAI_P20-1
DAI_P20-1
DAI_P20-1
(SDATA)
(SCLK)
(FS)
Rev. PrA | Page 31 of 48 | November 2004
Figure 20. SRC Serial Input Port Timing
t
SRCCLKW
t
SRCSFS
t
SRCSD
t
SAMPLE EDGE
SRCCLK
t
SRCHFS
t
SRCHD
Min
4
5.5
4
5.5
9
20
Max
ADSP-21367
Unit
ns
ns
ns
ns
ns
ns