ADSP-21367 Analog Devices, ADSP-21367 Datasheet - Page 2

• Manufacturer Part Number: ADSP-21367
• Description: SHARC Processor
• Manufacturer: Analog Devices

ADSP-21367
KEY FEATURES – PROCESSOR CORE
At 400 MHz (2.5 ns) core instruction rate, the ADSP-21367
2M bit on-chip SRAM (0.75M Bit in blocks 0 and 1, and 250K
6M bit on-chip mask-programmable ROM (3M bit in block 0
Dual Data Address Generators (DAGs) with modulo and bit-
Zero-overhead looping with single-cycle loop setup, provid-
Single Instruction Multiple Data (SIMD) architecture
Transfers between memory and core at a sustained 6.0G
INPUT/OUTPUT FEATURES
DMA Controller supports:
32-Bit Wide External Port Provides Glueless Connection to
Digital Audio Interface (DAI) includes eight serial ports, four
Digital Peripheral Interface (DPI) includes, three timers, two
Eight dual data line serial ports that operate at up to 50M
TDM support for telecommunications interfaces including
performs 2.4 GFLOPS/800 MMACS
Bit in blocks 2 and 3) for simultaneous access by the core
processor and DMA
and 3M bit in block 1)
reverse addressing
ing efficient program sequencing
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
Parallelism in busses and computational units allows: Sin-
bytes/s bandwidth at 400 MHz core instruction rate
34 zero-overhead DMA channels for transfers between
32-bit DMA transfers at core clock speed, in parallel with
both Synchronous (SDRAM) and Asynchronous Memory
Devices
Programmable wait state options: 2 to 31 SCLK cycles
Delay-line DMA engine maintains circular buffers in exter-
SDRAM accesses at 166MHz and Asynchronous accesses at
4 Memory Select lines allows multiple external memory
Precision Clock Generators, an Input Data Port, an S/PDIF
transceiver, an 8-channel asynchronous sample rate con-
verter, and a Signal Routing Unit
UARTs, two SPI ports, and a two wire interface port
Outputs of PCG's C and D can be driven on to DPI pins
bits/s on each data line — each has a clock, frame sync and
two data lines that can be configured as either a receiver or
transmitter pair
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
the assembly level
gle cycle executions (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
ADSP-21367 internal memory and a variety of
peripherals
full-speed processor execution
nal memory with tap/offset based reads
66MHz
devices
Rev. PrA | Page 2 of 48 | November 2004
Up to 16 TDM stream support, each with 128 channels per
Companding selection on a per channel basis in TDM mode
Input data port, configurable as eight channels of serial data
Signal routing unit provides configurable and flexible con-
2 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line /MS pin
1 Muxed Flag/IRQ /MS pin
DEDICATED AUDIO COMPONENTS
S/PDIF Compatible Digital Audio receiver/transmitter sup-
Sample Rate Converter (SRC) contains a Serial Input Port, De-
Pulse Width Modulation provides:
ROM Based Security features include:
PLL has a wide variety of software and hardware multi-
Dual voltage: 3.3 V I/O, 1.3 V core
Available in 256-ball BGA and 208-lead LQFP Packages (see
frame
or seven channels of serial data and a single channel of up
to a 20-bit wide parallel data
nections between all DAI/DPI components
ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left-justified, I
16, 18, 20 or 24-bit word widths (transmitter)
emphasis Filter, Sample Rate Converter (SRC) and Serial
Output Port providing up to -128db SNR performance.
Supports Left Justified, I
18 and 16-bit serial formats (input)
16 PWM outputs configured as four groups of four outputs
supports center-aligned or edge-aligned PWM waveforms
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
plier/divider ratios
Ordering Guide on page
access under program control to sensitive code
Preliminary Technical Data
2
S or right-justified serial data input with
2
47)
S, TDM and Right Justified 24, 20,