ADSP-21367 Analog Devices, ADSP-21367 Datasheet - Page 30

• Manufacturer Part Number: ADSP-21367
• Description: SHARC Processor
• Manufacturer: Analog Devices

ADSP-21367
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table
the IDP. For details on the operation of the IDP, see the IDP
chapter of the ADSP-2136x SHARC Processor Hardware Refer-
Table 24. Parallel Data Acquisition Port (PDAP)
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
SPCLKEN
HPCLKEN
PDSD
PDHD
PDCLKW
PDCLK
PDHLDD
PDSTRB
1
1
24. PDAP is the parallel mode operation of channel 0 of
1
1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
Clock Width
Clock Period
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
PDAP Strobe Pulse Width
(PDAP_STROBE)
(PDAP_CLKEN)
DAI_P20-1
DAI_P20-1
(PDAP_CLK)
DAI_P20-1
DATA
Rev. PrA | Page 30 of 48 | November 2004
Figure 19. PDAP Timing
t
PDCLKW
SAMPLE EDGE
t
SPCLKEN
t
PDSD
t
PDHLDD
ence. Note that the most significant 16 bits of external PDAP
data can be provided through either the parallel port AD15–0 or
the DAI_P20–5 pins. The remaining 4 bits can only be sourced
through DAI_P4–1. The timing below is valid at the
DAI_P20–1 pins or at the AD15–0 pins.
t
PDCLK
t
HPCLKEN
t
PDHD
t
PDSTRB
Min
2.5
2.5
2.5
2.5
7
24
2 × t
1 × t
Preliminary Technical Data
CCLK
CCLK
– 1
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns