ADSP-21367 Analog Devices, ADSP-21367 Datasheet - Page 29

• Manufacturer Part Number: ADSP-21367
• Description: SHARC Processor
• Manufacturer: Analog Devices

Preliminary Technical Data
Input Data Port
The timing requirements for the IDP are given in
Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 23. IDP
1
Parameter
Timing Requirements
t
t
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
SData Hold After SCLK Rising Edge
Clock Width
Clock Period
DAI_P20-1
DAI_P20-1
DAI_P20-1
(SDATA)
(SCLK)
(FS)
Rev. PrA | Page 29 of 48 | November 2004
Table
Figure 18. IDP Master Timing
23.IDP
t
IPDCLKW
t
SISFS
t
SISD
SAMPLE EDGE
t
IPDCLK
t
SIHFS
t
SIHD
Min
2.5
2.5
2.5
2.5
9
24
Max
ADSP-21367
Unit
ns
ns
ns
ns
ns
ns