ADSP-21367 Analog Devices, ADSP-21367 Datasheet - Page 14

• Manufacturer Part Number: ADSP-21367
• Description: SHARC Processor
• Manufacturer: Analog Devices

ADSP-21367
Table 3. Pin List
1
2
3
ADDRESS/DATA MODES
TBD
BOOT MODES
Table 4. Boot Mode Selection
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
For details on processor timing, see
Figure 3 on page
Table 5. Core Instruction Rate/ CLKIN Ratio Selection
BOOTCFG1–0
00
01
10
CLKCFG1–0
00
01
10
Pull-up is always enabled for ID - 000 in uniprocessor mode and ID- 001 in Multiprocessing mode.
Pull-up can be enabled/disabled, value of pull-up cannot be programmed.
OP is three-statable
Name
XTAL
CLKIN
CLKOUT
17.
Type
Output
Output
Booting Mode
SPI Slave Boot
SPI Master Boot
AMI boot via EPROM
Core to CLKIN Ratio
6:1
32:1
16:1
Timing Specifications
State During
and After
Reset
Rev. PrA | Page 14 of 48 | November 2004
and
Description
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21367 clock input.
It configures the ADSP-21367 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the ADSP-21367 to use the external clock source such as an
external clock oscillator. The core is clocked either by the PLL output or this clock input
depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or
operated below the specified frequency.
Local Clock Out. CLKOUT can also be configured as a reset out pin.The functionality
can be switched between the PLL output clock and reset out by setting bit 12 of the
PMCTREG register. The default is reset out.
Preliminary Technical Data