HW-SPAR3-SK-UNI-G Xilinx Inc, HW-SPAR3-SK-UNI-G Datasheet - Page 12

• Manufacturer Part Number: HW-SPAR3-SK-UNI-G
• Description: KIT STARTER SPARTAN-3
• Manufacturer: Xilinx Inc
• Series: Spartan-3r
• Type: FPGA Configurationr

Specifications of HW-SPAR3-SK-UNI-G

• Contents: Board, Cable, Software, Datasheets and User Manual
• For Use With/related Products: Spartan-3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1521

Address Bus Connections
12
R
The SRAM array forms either a single 256Kx32 SRAM memory or two independent
256Kx16 arrays. Both SRAM devices share common write-enable (WE#), output-enable
(OE#), and address (A[17:0]) signals. However, each device has a separate chip select
enable (CE#) control and individual byte-enable controls to select the high or low byte in
the 16-bit data word, UB and LB, respectively.
The 256Kx32 configuration is ideally suited to hold MicroBlaze instructions. However, it
alternately provides high-density data storage for a variety of applications, such as digital
signal processing (DSP), large data FIFOs, and graphics buffers.
Both 256Kx16 SRAMs share 18-bit address control lines, as shown in
address signals also connect to the A1 Expansion Connector (see
page
Table 2-1: External SRAM Address Bus Connections to Spartan-3 FPGA
47).
Address Bit
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
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FPGA Pin
M3
M4
K5
K3
H4
H3
G5
G4
N3
L3
E4
E3
L4
L5
F4
F3
J3
J4
Spartan-3 FPGA Starter Kit Board User Guide
A1 Expansion Connector Pin
Chapter 2: Fast, Asynchronous SRAM
35
33
34
31
32
29
30
27
28
25
26
23
24
14
12
10
8
6
“Expansion Connectors,”
UG130 (v1.2) June 20, 2008
Table
2-1. These