DK-NIOS-2C35N Altera, DK-NIOS-2C35N Datasheet - Page 53

• Manufacturer Part Number: DK-NIOS-2C35N
• Description: NIOS II KIT W/CYCLONE II EP2C35N
• Manufacturer: Altera
• Series: Cyclone® IIr
• Type: Nios®IIr

Specifications of DK-NIOS-2C35N

• Contents: Eval Board, Design Apps, Software, Cables and Accessories
• For Use With/related Products: Cyclone ll 2C35N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1698; DK-NIOS-2C35N

Clock Circuitry
Altera Corporation
May 2007
f
JTAG Connector to EPM7256AE Device (J5)
J5 connects to the JTAG pins (TCK, TDI, TDO, TMS, TRST) of the
EPM7256AE device (U3). Altera Quartus II software can perform in-
system programming (ISP) to reprogram the EPM7256AE device (U3)
with a new hardware image via an Altera download cable as shown in
Figure
1
Most users never need to reprogram the configuration controller design
in the EMP7256AE device. Reprogramming the configuration controller
can result in an inoperable development board.
To restore the board to its factory-programmed condition, see Appendix
B: Restoring the Factory Configuration.
Figure 2–20. JTAG Connector (J5) to MAX Device
The Nios development board includes a 50 MHz free-running oscillator
(Y2) and a zero-skew, point-to-point clock distribution network that
drives the FPGA (U62), the EPM7256AE configuration controller device
(U3), and pins on the PROTO1 & PROTO2 connectors. The zero-skew
buffer (U2) drives the clock distribution network using the free-running
50 MHz clock. Refer to
2–20.
The orientation of J5 is rotated 180 degrees compared to J24.
Reference Manual
Pin 1
Figure
J5
2–21.
Nios Development Board Cyclone II Edition
Board Components
2–41