DK-NIOS-2C35N Altera, DK-NIOS-2C35N Datasheet - Page 25

• Manufacturer Part Number: DK-NIOS-2C35N
• Description: NIOS II KIT W/CYCLONE II EP2C35N
• Manufacturer: Altera
• Series: Cyclone® IIr
• Type: Nios®IIr

Specifications of DK-NIOS-2C35N

• Contents: Eval Board, Design Apps, Software, Cables and Accessories
• For Use With/related Products: Cyclone ll 2C35N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1698; DK-NIOS-2C35N

Ethernet
MAC/PHY (U4) &
RJ45 Connector
(RJ1)
Altera Corporation
May 2007
The LAN91C111 chip (U4) is a 10/100 Ethernet media access control and
physical interface (MAC/PHY) chip. The control pins of U4 are
connected to the FPGA so that Nios II systems can access Ethernet
networks via the RJ-45 connector (RJ1) as shown in
Nios II development tools include hardware and software components
that allow Nios II processor systems to communicate with the
LAN91C111 Ethernet device.
Figure 2–4. Ethernet RJ-45 Connector
Refer to
device.
1
E26
J17
F18
G18
D18
E18
A19
B19
D20
D14
Y15
AA15
Table 2–9. Ethernet MAC/PHY Pin Table
FPGA Pin
Table 2–9
The Ethernet MAC/PHY device shares both address and data
connections with the flash memory.
Reference Manual
41
43
40
45
38
37
42
46
35
36
34
29
U4 Pin
for connections between the FPGA and the MAC/PHY
Address Enable
Synchronous Ready
VL Bus Access
Local Device
IO Char Ready
Address Strobe
Local Bus Clock
Ready/Return
Bus Cycle
Write/Read
Bus Chip Select
Interrupt
Nios Development Board Cyclone II Edition
Pin Function
RJ1
U4
enet_aen
enet_srdy_n
enet_vlbus_n
enet_ldev_n
enet_iochrdy
enet_ads_n
enet_lclk
enet_rdyrtn_n
enet_cycle_n
enet_w_r_n
enet_datacs_n
enet_intr0
Figure
Board Net Name
Board Components
2–4. The
(1)
2–13