DK-NIOS-2C35N Altera, DK-NIOS-2C35N Datasheet - Page 21

• Manufacturer Part Number: DK-NIOS-2C35N
• Description: NIOS II KIT W/CYCLONE II EP2C35N
• Manufacturer: Altera
• Series: Cyclone® IIr
• Type: Nios®IIr

Specifications of DK-NIOS-2C35N

• Contents: Eval Board, Design Apps, Software, Cables and Accessories
• For Use With/related Products: Cyclone ll 2C35N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1698; DK-NIOS-2C35N

DDR SDRAM
Chip (U63)
Altera Corporation
May 2007
f
The following pins on U74 have fixed connections, which restricts the
usable modes of operation:
■
■
■
■
See www.cypress.com for detailed information about the SSRAM chip.
U63 is a Micron DDR SDRAM chip. Depending on the board revision, the
part number is MT46V16M16TG or MT46V16M16P-6T. The DDR
SDRAM pins are connected to the FPGA as shown in
provides a DDR SDRAM controller that allows a Nios II processor to
access the DDR SDRAM device as a large, linearly-addressable memory.
K9
E5
R2
R3
R4
P7
P6
T2
T3
R6
W2
W1
U6
U7
U5
Y1
Table 2–6. SSRAM Pin Table (Continued)
Table 2–7. DDR SDRAM Pin Table
FPGA Pin
MODE is pulled low to enable Linear Burst
ZZ is pulled low to leave the chip enabled
GLOBALW_n is pulled high to disable the global write
CE2 and CE3_n are wired high and low respectively to be enabled
and to make CE1_n the master chip enable
FPGA Pin
Reference Manual
2
4
5
7
8
10
11
13
54
56
57
59
60
62
88
89
U63 Pin
U74 Pin
Nios Development Board Cyclone II Edition
sdram_dq0
sdram_dq1
sdram_dq2
sdram_dq3
sdram_dq4
sdram_dq5
sdram_dq6
sdram_dq7
sdram_dq8
sdram_dq9
sdram_dq10
sdram_dq11
sdram_dq12
sdram_dq13
GW_n
CLK
Board Net Name
Pin Function
Table
Board Components
ssram_gw_n
sram_clk
Board Net Name
2–7. Altera
2–9