DK-NIOS-2C35N Altera, DK-NIOS-2C35N Datasheet - Page 27

• Manufacturer Part Number: DK-NIOS-2C35N
• Description: NIOS II KIT W/CYCLONE II EP2C35N
• Manufacturer: Altera
• Series: Cyclone® IIr
• Type: Nios®IIr

Specifications of DK-NIOS-2C35N

• Contents: Eval Board, Design Apps, Software, Cables and Accessories
• For Use With/related Products: Cyclone ll 2C35N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1698; DK-NIOS-2C35N

Serial Connector
(J19)
Altera Corporation
May 2007
f
See www.smsc.com for detailed information about the LAN91C111
device.
J19 is a standard DB-9 serial connector, and is typically used for
communication between the FPGA and a host computer via an RS-232
serial cable. Level-shifting buffer (U52) is used between J19 and the
FPGA, because the FPGA device cannot interface to RS-232 voltage levels
directly.
J19 is able to transmit all RS-232 signals. Alternately, the FPGA design can
use only the signals it needs, such as J19’s RXD and TXD pins. LEDs are
connected to the RXD and TXD signals and visually indicate when data
is being transmitted or received.
connections between the serial connectors and the FPGA.
Note to
(1)
A9
C10
D10
B10
A10
E12
D12
J13
J14
F12
G12
J10
J11
C11
B11
C12
B12
D6
G11
Table 2–9. Ethernet MAC/PHY Pin Table (Continued)
FPGA Pin
Nets fe_a0 and fe_a16 to fe_a23 do not connect to U4.
Table
2–9:
Reference Manual
70
69
68
66
65
64
63
61
60
59
58
56
55
54
53
51
50
49
48
U4 Pin
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Data Line
Nios Development Board Cyclone II Edition
Pin Function
Figure 6
and
Table 2–10
fe_d13
fe_d14
fe_d15
fe_d16
fe_d17
fe_d18
fe_d19
fe_d20
fe_d21
fe_d22
fe_d23
fe_d24
fe_d25
fe_d26
fe_d27
fe_d28
fe_d29
fe_d30
fe_d31
Board Net Name
Board Components
show the pin
(1)
2–15