DK-NIOS-2C35N Altera, DK-NIOS-2C35N Datasheet - Page 14

• Manufacturer Part Number: DK-NIOS-2C35N
• Description: NIOS II KIT W/CYCLONE II EP2C35N
• Manufacturer: Altera
• Series: Cyclone® IIr
• Type: Nios®IIr

Specifications of DK-NIOS-2C35N

• Contents: Eval Board, Design Apps, Software, Cables and Accessories
• For Use With/related Products: Cyclone ll 2C35N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1698; DK-NIOS-2C35N

Board Components
2–2
Nios Development Board Cyclone II Edition
Memory
U74
U5, LED7
U63
Connections & Interfaces
U4, RJ1
J19
PROTO1 (J11, J12, J13) Expansion prototype
PROTO2 (J15, J16, J17) Expansion prototype
CON3
JH1, JH2
J25
TP1 – TP8
J24
J5
J27
Configuration & Reset
U3
U69
SW8
Table 2–1. Nios Development Board, Cyclone II Edition Components & Interfaces (Continued)
Board Designation
SSRAM memory
Flash memory
DDR SDRAM memory
Ethernet MAC/PHY
Serial connector
connector
connector
CompactFlash connector
PMC connector
Mictor connector
Test Points
JTAG connector
JTAG connector
EPCS configuration header
MAX Configuration controller Altera MAX EPM7256AE device used to configure
Serial configuration device
CPU Reset button
Name
Reference Manual
2 Mbytes of synchronous SRAM.
16 Mbytes of nonvolatile memory for use by both the
FPGA and the configuration controller. LED7 lights
whenever the flash chip-enable is asserted.
32 Mbytes of DDR SDRAM.
10/100 Ethernet MAC/PHY chip connected to an RJ-
45 Ethernet connector.
RS-232 serial connector with 5 V-tolerant buffers.
Supports all RS-232 signals.
Expansion headers connecting to 41 I/O pins on the
FPGA. Supplies 3.3V and 5.0V for use by a daughter
card.
Expansion headers connecting to 41 I/O pins on the
FPGA. Supplies 3.3V and 5.0V for use by a daughter
card.
CompactFlash connector for memory expansion.
Expansion connector for a PCI mezzanine card.
Mictor connector providing access to 27 I/O pins on
the FPGA. Allows debugging Nios II systems using a
First Silicon Solutions (FS2) debug probe.
Test points providing access to eight FPGA I/O pins.
JTAG connection to the FPGA allowing hardware
configuration using the
Quartus
Nios II IDE.
JTAG connection to the MAX
controller.
Connects to the EPCS serial configuration device for
in-system programming.
the FPGA from flash memory.
Altera EPCS64 low-cost serial configuration device to
configure the FPGA.
Push-button switch to reboot the Nios II processor
configured in the FPGA.
®
II software and software debug using the
Description
®
configuration
Altera Corporation
May 2007