IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 9

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Altera Corporation
November 2009
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Hardware accelerators generated by the C2H Compiler have the
following characteristics:
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Design Abstraction and the Rise of C for FPGAs
There is much interest in “C-to-gates” tools that promise a practical
method to create hardware logic directly from C code. However, early
attempts have had limited success gaining acceptance in the design
community. This section discusses the historical background of the
C2H Compiler, and looks at the questions “why is this methodology a
good idea?” and “why now?”
C compilers and FPGA design tools have evolved along separate paths,
but both are founded on the same premise: Higher levels of design
abstraction enable engineers to create designs of greater size and
complexity. Simultaneous with this evolution, Moore's law has delivered
chips of increasing density and complexity, such as FPGAs capable of
Straightforward C-to-hardware mapping – The C2H Compiler maps
each element of C syntax to a defined hardware structure, giving you
control over the structure of your hardware accelerator.
Integration with C language development environments for the
Nios II processor, including the Nios II integrated development
environment (IDE), and the Nios II software build tools. You control
the C2H Compiler with the Nios II C development tools. You do not
need to learn a new environment to use the C2H Compiler.
Based on SOPC Builder and Avalon system interconnect fabric – The
C2H Compiler uses SOPC Builder as the infrastructure to connect
hardware accelerators into Nios II systems. A C2H accelerator
becomes a component within an existing Nios II system. SOPC
Builder automatically generates system interconnect fabric to
connect the accelerator to the system, saving you the time of
manually integrating the hardware accelerator.
Reporting of generated results – The C2H Compiler produces a
detailed report of hardware structure, resource usage, and
throughput.
Parallel scheduling – The C2H Compiler recognizes events that can
occur in parallel. Independent statements are performed
simultaneously in hardware.
Direct memory access – Accelerators access the same memories that
the Nios II processor does during execution.
Loop pipelining – The C2H Compiler pipelines the logic
implemented for loops, based on memory access latency and the
amount of code that operates in parallel.
Memory access pipelining – The C2H Compiler pipelines memory
accesses to reduce the effects of memory latency.
9.1
Introduction to the C2H Compiler
Nios II C2H Compiler User Guide
1–3