IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 78

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Scheduling
Example 3–32. Early Scheduling of Read Operation with Latency
#pragma altera_accelerate connect_variable \
int foo(int *ptr_in, int x, int y, int z)
{
}
3–38
Nios II C2H Compiler User Guide
int xy
int xy_plus_z = xy + z;
int ptr_data
int prod
return prod;
foo/ptr_in to \
my_memory_with_two_cycles_read_latency
= x * y;
= *ptr_in;
= ptr_data * xy_plus_z;
and mitigate the effects of memory latency. Through close integration
with SOPC Builder, the C2H Compiler can determine the latency
characteristics of the slave ports connected to the accelerator. The
C2H Compiler generates logic to maximize bandwidth for the specific
memories in the system.
Avalon-MM pipelined read transfers increase the bandwidth for
synchronous slave ports that require several cycles of latency to return
data for the first access, but can return data every cycle thereafter. Using
pipelined read transfers, a slave port can begin a new transfer before data
from the previous transfer returns. There are only pipelined read
transfers; Avalon-MM write transfers do not benefit from pipelined
functionality.
The C2H Compiler takes memory latency into account when scheduling
operations, allowing an accelerator to perform nondependent operations
while waiting for data to return from a memory with latency. The master
ports associated with a pointer might connect to multiple slave ports with
different latency properties. In this case, the C2H Compiler uses the
maximum latency of all slave ports.
Figure 3–18
Example
connect a pointer named ptr_in to a memory with two cycles of read
latency. (Refer to section
3–32. This example uses the connection pragma to exclusively
shows the dependency graph for function foo(), shown in
9.1
“Master-Slave Connections” on page
Altera Corporation
November 2009
3–23.)