IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 16

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

C2H Compiler Concepts
1–10
Nios II C2H Compiler User Guide
The accelerator's connections are managed by the C2H Compiler. You can
manually customize the connections using pragma directives in the
accelerated C code.
C2H Compiler pragma usage. You cannot edit the accelerator's
connections in the SOPC Builder GUI.
Generation of a Hardware Accelerator
The C2H compilation flow shares commonalities with a conventional C
compiler, but the scheduling of statements, optimization, and object
generation is different. When generating a hardware accelerator, the
C2H Compiler does the following:
1.
2.
3.
4.
5.
6.
7.
The generated accelerator logic includes the following:
■
■
■
Runs the GNU GCC preprocessor to evaluate macros, includes, and
other preprocessing directives.
Parses code.
Creates a graph of data dependencies.
Performs some optimizations.
Determines the best sequence in which to perform each operation.
Generates an object file for the hardware accelerator. This object file
is a synthesizable HDL file.
Generates a C wrapper function that isolates and hides the details of
how the Nios II processor interacts with the hardware accelerator.
The wrapper function is a C file that replaces the original C function
at software link time.
One or more state machines that manage the sequence of operations
defined by the C function. On any clock cycle, an arbitrary number
of computations and memory accesses can happen simultaneously,
orchestrated by the state machines.
One or more Avalon Memory-Mapped (Avalon-MM) master ports,
which fetch and store data as required by the state machines.
An Avalon-MM slave port and a set of memory-mapped registers
that allow the processor to set up, start, and stop the accelerator.
Chapter 6, Pragma
9.1
Reference, describes
Altera Corporation
November 2009