IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 103

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Figure 4–3. Multiplier Resources
Altera Corporation
November 2009
1
The pipeline value associated with the resource specifies the number of
clock cycles that the hardware logic requires for the calculation to
complete. Pipelined logic can typically operate at higher clock
frequencies due to the additional latency introduced. The C2H Compiler
factors in the pipelining of the hardware and schedules the accelerated
function accordingly to maximize data throughput. When the report does
not show a pipeline value for a resource, that means that the operator is
purely combinational, with no latency.
Nios II C2H Compiler User Guide
The resource usage does not reflect the final resource utilization
of the compiled hardware. When ANSI C code is compiled,
small integer data types are promoted to the int data type. In
Figure 4–3
though the operands are short (16 bits). The C2H Compiler
performs the same integer data promotion, creating a 32-bit
multiplier. When the Quartus II software compiles the hardware
design, the synthesized multiplier is 16 bits in width.
we can see that the multiplier is 32 bits wide even
9.1
Understanding the C2H View
4–9