IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet
IPT-C2H-NIOS
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IPT-C2H-NIOS Summary of contents
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... Innovation Drive San Jose, CA 95134 www.altera.com Nios II C2H Compiler User Guide Nios II C2H Compiler Version: Document Date: 9.1 November 2009 ...
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... Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U ...
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... Run the Project as Software Only .................................................................................................. 2–7 Create and Configure a Hardware Accelerator ........................................................................... 2–8 Rebuild the Project ......................................................................................................................... 2–10 Observe Results in the Report File ............................................................................................... 2–11 Observe the Accelerator in SOPC Builder .................................................................................. 2–14 Run the Project with the Accelerator ........................................................................................... 2–14 Remove the Accelerator ................................................................................................................ 2–15 Altera Corporation Contents 9.1 iii ...
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... Local vs. Non-Local Variables ...................................................................................................... 3–13 Scalar Variables ............................................................................................................................... 3–14 Memory Accesses ................................................................................................................................ 3–15 Indirection Operator (Pointer Dereference) ............................................................................... 3–16 Avalon-MM Master Port Signal Generation .............................................................................. 3–20 Array Subscript Operator .............................................................................................................. 3–26 Structure and Union Operators .................................................................................................... 3–28 Scheduling ............................................................................................................................................ 3–30 Scheduling Concepts for Hardware Accelerators ..................................................................... 3–30 Pointer Aliasing .............................................................................................................................. 3–32 Read Operations with Latency ..................................................................................................... 3– ...
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... Chapter 7. ANSI C Compliance and Restrictions Introduction ............................................................................................................................................ 7–1 Language ................................................................................................................................................. 7–1 Declarations ....................................................................................................................................... 7–1 Expressions ........................................................................................................................................ 7–3 Functions ........................................................................................................................................... 7–4 Miscellaneous Unsupported Features ........................................................................................... 7–8 Other Restrictions .................................................................................................................................. 7–9 Additional Information Referenced Documents ............................................................................................................................. 1 Revision History ........................................................................................................................................ 2 How to Contact Altera .............................................................................................................................. 3 Typographic Conventions ........................................................................................................................ 3 Altera Corporation 9.1 Nios II C2H Compiler User Guide Contents v ...
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... Contents vi Nios II C2H Compiler User Guide 9.1 Altera Corporation ...
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... A hardware accelerator is a block of logic that implements a C function in hardware, which often improves the execution performance by an order of magnitude. Using the C2H Compiler, you can develop and debug an algorithm in C targeting an Altera quickly convert the C code to a hardware accelerator implemented in a field programmable gate array (FPGA). ...
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... To benefit from this user guide, you do not need expert in these tools, and you do not need an understanding of any particular Altera FPGA family. However, at least a basic understanding of each tool is required to use the C2H Compiler practically. Introduction This chapter introduces the Nios II C2H Compiler. The sections in this ...
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... Simultaneous with this evolution, Moore's law has delivered chips of increasing density and complexity, such as FPGAs capable of Altera Corporation November 2009 Straightforward C-to-hardware mapping – The C2H Compiler maps each element of C syntax to a defined hardware structure, giving you control over the structure of your hardware accelerator ...
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... The application of these techniques relies on real-world tools to implement them. Consequently, the acceptance of these techniques has grown as system integration tools, such as Altera's SOPC Builder, have matured and gained acceptance fortunate coincidence that these techniques also directly benefit C-to-gates methodologies. Flexibility of hardware architecture and ease of implementation are at the heart of the appeal of C-to-gates tools. 1– ...
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... The Nios II C-to-Hardware Acceleration (C2H) Compiler represents Altera's next step in the evolution of embedded systems design. The C2H Compiler uses the infrastructure provided by SOPC Builder and the Nios II processor, and adds a higher level of abstraction: converting C functions directly to hardware. What to Expect From the C2H Compiler The C2H Compiler is not designed to build all types of FPGA systems ...
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... The Nios II IDE allows you to carry out the following important tasks: ■ ■ ■ Altera recommends creating new C2H systems with the Nios II IDE. f For information about using the Nios II IDE, refer to the Integrated Development Environment Developer's about Nios II tool flows, refer to “Development Flows for Creating Nios II Programs” ...
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... As a result, you have the freedom to design iteratively, and explore multiple architectures. By contrast, writing a hardware accelerator by hand in a hardware description language (HDL) would require a significant amount of time to create the logic design and integrate it into the system. Changing the functional or performance requirements of hand-written HDL blocks can significantly impact design time ...
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... The resulting hardware accelerator then replaces only processor-intensive tasks, rather than setup or control tasks which the processor can implement efficiently. 1–8 Nios II C2H Compiler User Guide 9.1 Altera Corporation November 2009 ...
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... SOPC Builder component. If there is more than one accelerator in the system, multiple accelerators appear in SOPC Builder. Accelerators are separate from the Nios II processor but can access the same memory devices that the Nios II processor can. Altera Corporation November 2009 shows the architecture of a simple Nios II processor system Hardware ...
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... One or more Avalon Memory-Mapped (Avalon-MM) master ports, which fetch and store data as required by the state machines. An Avalon-MM slave port and a set of memory-mapped registers that allow the processor to set up, start, and stop the accelerator. 9.1 Reference, describes Altera Corporation November 2009 ...
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... The following are examples of how the C2H Compiler translates C to hardware: ■ ■ ■ ■ Altera Corporation November 2009 Sets up parameters for the accelerator, similar to passing variables to the original, unaccelerated function. Optionally flushes the processor's data cache to avoid cache coherency problems. Flushing the data cache might be necessary if the accelerator accesses the same memory that the processor does ...
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... The C2H Compiler creates only one hardware instance of the subfunction, regardless of how many times the subfunction is called within the top-level function. Isolating accelerated C code into a subfunction provides a method of creating a shared hardware resource within an accelerator. Chapter 3, C-to-Hardware Mapping Reference 9.1 for complete Altera Corporation November 2009 ...
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... Checksum calculations are typically a time-consuming part stack, because all data transmitted and received must be validated, which requires the processor to loop through all bytes. Altera Corporation November 2009 They contain a relatively small and simple loop or set of nested loops. ...
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... Code that contains many data or control dependencies must perform many sequential operations, and is a poor candidate for acceleration. A large number of dependencies makes it difficult for the C2H Compiler to fully optimize loops. Processors are designed to perform such operations efficiently. 9.1 Altera Corporation November 2009 ...
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... If you are starting with an existing code base that you want to accelerate, the C2H Compiler can benefit you to the Altera Corporation November 2009 If the code contains C syntax not supported by the C2H Compiler, it cannot be accelerated ...
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... Now that you understand the underlying concepts of the Nios II C-to-Hardware Acceleration Compiler, you are ready for hands-on experience accelerating designs. Tutorialdescribes the C2H Compiler design flow, and gives step-by-step instructions to accelerate your first design. Altera also provides tutorials and application notes to deepen your understanding of the C2H Compiler. f Refer to the Nios II literature page for further C2H Compiler documentation: www ...
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... Nios II design flow. f For introductory information on designing with the Nios II processor, refer to the Nios II literature page at http://www.altera.com/literature/lit-nio2.jsp, and to the Nios II Software Development Tutorial available in the Nios II integrated development environment (IDE) help system. C2H Compiler This section discusses the design flow to create a hardware accelerator with the C2H Compiler ...
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... This tutorial does not describe techniques for optimizing hardware accelerator performance. For further information on optimizing C2H Compiler results, refer to the C2H Compiler Software Requirements The C2H Compiler in evaluation mode is installed as part of the Altera Quartus Complete Design Suite free from the Altera website. Visit www.altera.com 2–2 ...
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... Nios II hardware design. The output is a set of hardware description language (HDL) files (.v or .vhd) and an SOPC Builder system file (.sopcinfo) defining your system: Nios II processor cores, peripherals, accelerators, on-chip memory, and interfaces to off-chip memory. Quartus II software – ...
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... The hardware design for this tutorial is based on the standard hardware example design provided with the Nios II EDS. The software design file named dma_c2h_tutorial.c, which is available for download from the Altera website. You can run the tutorial design on any Nios development board available from Altera. 2–4 Nios II C2H Compiler User Guide “ ...
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... Calls the do_dma() function 100 times Checks the copied data to ensure there were no errors Frees the two allocated buffers Connect your Nios development board to power, and connect the board to your host computer with an Altera download cable. 9.1 Getting Started Tutorial http://www.altera.com/ ...
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... Click Start. The programmer downloads the configuration data to the FPGA Start is not enabled, click Hardware Setup to configure your JTAG download cable. Start the Nios II IDE. If the Workspace Launcher dialog box appears, click OK to accept the default workspace. 9.1 Altera Corporation November 2009 ...
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... To run the program, perform the following steps: 1. Altera Corporation November 2009 If the Welcome to the Altera Nios II IDE page displays, close it to view the workbench. Create a new C/C++ Application project the File menu, point to New and click C/C++ Application. ...
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... C2H Compiler is forced to rebuild the accelerator, even if you edit unrelated code. Set the build options for the new accelerator, as shown in a. Click the + icon to expand c2h_tutorial_sw in the C2H view. 9.1 Example 2–1 shows Figure 2–1. Altera Corporation November 2009 ...
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... Figure 2–1. Setting the Build Options for the Accelerator Altera Corporation November 2009 b. Turn on Build software, generate SOPC Builder system, and run Quartus II compilation. When you build the project in the Nios II IDE, this option causes the C2H Compiler to invoke SOPC Builder and the Quartus II software in the background to generate a new ...
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... Nios II software build tools, these files are located in your software application directory.) c2h_accelerator_base_addresses.h — This is the C2H accelerator base addresses header file located in the same directory as alt_c2h_<function name>.c. 9.1 Altera Corporation November 2009 ...
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... Inspect the report by performing the following steps Altera Corporation November 2009 If you copy or move a C2H project to a different directory, you must make sure you have the generated C source files and C2H makefile fragments in the new location. If you regenerate your accelerator in the new location, the C2H Compiler recreates these files for you ...
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... In this example, there are two master ports: one for dereferencing the read pointer, *source_ptr, and one for dereferencing the write pointer, *dest_ptr. 2–12 Nios II C2H Compiler User Guide Expand the Resources section and all subsections, as shown in Figure 2–2. 9.1 Altera Corporation November 2009 ...
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... CPLI value of 1. (These values can differ, depending on the memory latency on your target board.) These numbers indicate that the pipeline takes 13 cycles to fill; once the pipeline is filled, the pipeline generates a new result every cycle. 1 Altera Corporation November 2009 Expand the Performance section and all subsections, as shown in Figure 2–3. ...
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... Builder system file without saving it. If you save the out-of-date file, you overwrite your accelerator-enhanced system file. Return to the Quartus II window not already open. Configure the FPGA with the new .sof file that contains the accelerator. 9.1 Tutorial. Altera Corporation November 2009 ...
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... Total time: 8470 ms Remove the Accelerator You can remove an accelerator from a design by performing the following steps in the Nios II IDE. 1. Altera Corporation November 2009 a. If the Programmer window is not still open, on the Tools menu click Programmer. The Programmer window lists the file standard ...
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... Do not use SOPC Builder to manually delete the component from the system. If you delete the component from the SOPC Builder system using the SOPC Builder GUI, the C2H Compiler produces undefined results the next time you build the software project. 9.1 Altera Corporation November 2009 ...
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... To get a better understanding of how the C2H Compiler translates C to hardware, read that, for further information on optimizing C2H Compiler results, refer to the Altera Corporation November 2009 It is common to be able to improve first-pass performance results significantly by optimizing the C code and system architecture. ...
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... Next Steps 2–18 Nios II C2H Compiler User Guide 9.1 Altera Corporation November 2009 ...
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... MAC() shown in Example 3–1. Function with Arithmetic and Logical Operators long long MAC (int* a, int* b, int len) { long long result = 0; while (len > result += *a++ * *b++; len--; } return result; } Altera Corporation November 2009 3. C-to-Hardware Mapping ® II C-to-Hardware Acceleration Example 3–1. 9.1 Reference 3–1 ...
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... Avalon-MM master port to read data (two total for *a++ ). Refer to section *b++ “Indirection Operator (Pointer Dereference)” on page 3–16. 32-bit up-counter (two total for ++ and ) *a++ *b++ 32x32=64-bit multiplier 32-bit down-counter -- Figure 3–1 shows the Altera Corporation November 2009 and ...
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... Altera Corporation November 2009 Assignments that require zero logic elements in hardware Assignments that use multiple registers to pipeline complex arithmetic operations Table 3–2 lists the applicable operators and Description Right bit-wise shift >> Left bit-wise shift << bit-wise AND & bit-wise inclusive OR ...
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... Operator The general rule "one registered assignment for every = operator" can be amended to read, "one registered assignment for every = operator or complex arithmetic operator". 3–4 Nios II C2H Compiler User Guide 3–3. Some arithmetic operations, such as multiplication, use a large Description Multiplication * Division / Modulus % Right bit-wise shift > ...
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... In other words loop exists within an outer loop, the state machine for the outer loop stalls each iteration and waits for the inner loop state machine to complete. Altera Corporation November 2009 shows the hardware that results from the following statement: int foo = ...
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... Logic to perform all operations in the then block Logic to perform all operations in the else block Selection logic that determines which result to use shows the circuit that results from the code in 9.1 Example 3–2. Altera Corporation November 2009 ...
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... Figure 3–5 Example 3–3. if Logic Without else if (foo > bar) foo += bar; Altera Corporation November 2009 C-to-Hardware Mapping Reference shows the circuit that results from the code in 9.1 Nios II C2H Compiler User Guide Example 3– ...
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... Conditional Operator ?: The ?: (conditional) operator is functionally equivalent to the if-else statement, but the placement of registers is different. The condition logic and selection logic compute in the same clock cycle, and the result is registered. 3–8 Nios II C2H Compiler User Guide 9.1 Altera Corporation November 2009 ...
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... The C2H Compiler converts switch statements to functionally- equivalent nested if-else statements, and then translates the if-else statements to hardware, as described in section page Altera Corporation November 2009 shows the circuit that results from the following code: foo = (foo > bar) ? (foo + bar) : (foo * bar); ...
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... Table 3–4. 9.1 if-else Implementation if (byte_select == 1) out = in & 0x0000ff00; else if (byte_select == 2) out = in & 0x00ff0000; else if (byte_select == 3) out = in & 0xff000000; else out = in & 0x000000ff; Altera Corporation November 2009 ...
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... However, the subfunction is a private resource exclusive to the calling function. In other words, if multiple separate, accelerated functions call a common subfunction, the C2H Compiler creates separate instances of the subfunction logic. Altera Corporation November 2009 C-to-Hardware Mapping Reference Figure 3–8 on page 3– ...
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... Nios II C2H Compiler User Guide shows an example of a subfunction called by two different void bar(int *data_in, int *data_out) { ... foobar_sub(); ... foobar_sub(); ... } shows the hardware structure of the accelerators resulting Table 3–5. Logic for the function foobar_sub() exists 9.1 Altera Corporation November 2009 ...
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... Altera Corporation November 2009 C-to-Hardware Mapping Reference Example 3–4 // product is local to mac(). 9.1 Nios II C2H Compiler User Guide 3–13 ...
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... Nios II C2H Compiler User Guide Example 3–5 demonstrates some examples of scalar demonstrates some examples of nonscalar variables. The following constructs are declared in the driver file (and therefore in the processor's data memory), and passed into the accelerator by reference: 9.1 Altera Corporation November 2009 ...
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... Hardware accelerators generated by the C2H Compiler use Avalon-MM master ports to access memory, similar to the Nios II processor and other Accesses SOPC Builder components. The Altera tool handles the task of physically connecting both accelerators and processors to memory, and creating arbitration logic result, the ...
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... Nios II C2H Compiler User Guide Specification. Pointer dereference (* operator) Index into an array ([ operator) Index into a struct or union (. or -> operator) Usage of a global or static variable demonstrates various lines of code that generate a master 9.1 and the Avalon Memory- Altera Corporation November 2009 ...
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... Because the array subscript operation and the member operation for structures and unions can be expressed in terms of an address computation and a pointer dereference, this section is fundamental to understanding how arrays, structures, and unions translate to hardware as well. Creation of Avalon-MM master ports In general, the C2H Compiler creates a master port on the accelerator for every instance of the indirection operator ...
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... Nios II C2H Compiler User Guide shows two dereferences that are identical inside of a loop. demonstrates a case of non equivalent pointers. is similar to Example 3–10, but packed_data increments 9.1 Altera Corporation November 2009 ...
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... The volatile type qualifier forces the variable to be evaluated strictly according to the rules of the language. volatile is normally used to access non-memory peripherals, such as timers and communication devices. 1 Altera Corporation November 2009 C-to-Hardware Mapping Reference demonstrates another case of non equivalent pointers. is similar to Example 3– ...
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... Nios II C2H Compiler User Guide demonstrates the use of volatile to guarantee multiple, Example 3–14 demonstrates two sections of code that are Logic to compute the address signal For write transfers only, logic to compute the write-data signal Logic to control the read-enable or write-enable signal 9.1 Altera Corporation November 2009 ...
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... Avalon-MM master port. As soon as the address signal ptr_to_int_i_address is valid, read-enable control logic asserts the signal ptr_to_int_i_read, which initiates a transfer on the master Altera Corporation November 2009 int j = *(ptr_to_int + i); ptr_to_int_i_addr = ptr_to_int + i * sizeof(int); shows an example of the logic created for this pointer 3– ...
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... Figure 3–10 dereference for a write operation. Figure 3–10. Data Generation for a Write Operation 3–22 Nios II C2H Compiler User Guide “Read Operations with Latency” on page shows an example of the logic created for this pointer 9.1 3–37.) Altera Corporation November 2009 ...
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... By using pragmas, you can write directives to optimize the C2H Compiler results, without making the C code incompatible with other compilers. Altera Corporation November 2009 shows the logic created for the following write operation to a “Assignments” on page *(ptr_to_int + ...
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... For more information, refer to section 3–24 Nios II C2H Compiler User Guide . MAX #pragma altera_accelerate connect_variable \ <function name>/<variable name> to <module>[/<slave name>] 9 MAX “Pointer Aliasing” on page 3–32. ...
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... Example 3–16. Pragma Connecting a Master Port to Multiple Slave Ports #pragma altera_accelerate connect_variable foo/my_ptr to onchip_buffer_0 #pragma altera_accelerate connect_variable foo/my_ptr to ext_ram_bridge #pragma altera_accelerate connect_variable foo/my_ptr to sdram #pragma altera_accelerate connect_variable foo/my_ptr to \ int foo(int *my_ptr) { int x = *my_ptr; my_ptr[8] = 23; ...
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... Nios II C2H Compiler User Guide connects the variable x in function myfunc to the memory #pragma altera_accelerate \ enable_flow_control_for_pointer \ <function name>/<variable name> Specification. The definition of the subscript operator [] is that E1[E2] is identical to (*((E1)+(E2))). 9.1 Avalon Memory- Altera Corporation November 2009 ...
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... A series of subscript operations that index into all N dimensions dimensional array is equivalent to an indirection operation, which creates an Avalon-MM master port. generate an Avalon-MM master port to dereference an array variable. ...
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... Example 3–20. Converted struct Member Operation *((pointer_to_type_of_a) ((void *)&mystruct + offset_of_a)) Similarly, the union member operation (myunion.a) is equivalent to Example Example 3–21. Converted union Member Operation *((pointer_to_type_of_a)(&myunion)) 3–28 Nios II C2H Compiler User Guide 3–16. 3–20. 3–21. 9.1 “Indirection Operator 3–14. Altera Corporation November 2009 ...
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... Example 3–23. Converted struct Pointer Operation *((pointer_to_type_of_a) ((void *)mystruct + offset_of_a)) The structure pointer operation on a union (e.g. myunion->a) is equivalent to Example 3–24. Converted union Pointer Operation *((pointer_to_type_of_a)myunion) Altera Corporation November 2009 *((int *)((void *)&my_struct + 2*sizeof(int))) Example 3–23. Example 3–24. 9.1 ...
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... C2H Compiler translates individual operations, assignments, and memory accesses to atomic functional units in 3–30 Nios II C2H Compiler User Guide *((int *)((void *)mystruct + 2*sizeof(int))) “One-to-One C-to-Hardware Mapping” on page 3–13, and “Memory Accesses” on page 3–15 9.1 Example 3–25. 3–1, “Variable Altera Corporation November 2009 ...
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... Figure 3–12 Example 3–26. Data Dependency int foo(int a, int b, int c) { int int int return z; } Altera Corporation November 2009 Accelerated function (top level) Loop Subfunction shows the dependency graph for 9.1 C-to-Hardware Mapping Reference Example 3–26. ...
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... Pointer aliasing is another form of data dependency that the C2H Compiler must consider. Any read or write operation with a pointer is dependent on all pointer write- 3–32 Nios II C2H Compiler User Guide Figure 3–13 shows how the C2H Compiler 9.1 Altera Corporation November 2009 ...
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... The dependency graph shows that the read operation from ptr_b depends on the write operation to ptr_a. This is not a dependency on the variable ptr_a, but rather a dependency on a location in memory that is unknown at Altera Corporation November 2009 C-to-Hardware Mapping Reference shows the dependency graph for 9 ...
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... Pointer Type Qualifier to Break Dependencies _ _ demonstrates several pointers declared using the The qualifier comes after the *; __restrict__ qualifies the pointer type, not the type that the pointer points to. shows the dependency graph for 9.1 Example 3–29, which uses Altera Corporation November 2009 ...
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... Example 3–30. Pointers Always Depend on Themselves void foo(int * _ _ restrict_ _ my_ptr, int offset_a, int offset_b) { int my_ptr[offset_a]; my_ptr[offset_a my_ptr[offset_b]; my_ptrb[offset_b Altera Corporation November 2009 C-to-Hardware Mapping Reference shows the dependency graph for 9.1 Nios II C2H Compiler User Guide Example 3–30. 3–35 ...
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... Nios II C2H Compiler User Guide shows the dependency graph for Figure 3–16. 9.1 Example 3–31, which Altera Corporation November 2009 ...
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... Inherently, an operation cannot proceed until the data for the operation arrives, which depends on memory latency. The C2H Compiler generates logic within hardware accelerators to manage Altera Corporation November 2009 C-to-Hardware Mapping Reference If a data structure is referenced by two pointers and one or more of them is restrict-qualified, the ISO C 99 standard specifies that the behavior is undefined ...
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... Figure 3–18 Example connect a pointer named ptr_in to a memory with two cycles of read latency. (Refer to section Example 3–32. Early Scheduling of Read Operation with Latency #pragma altera_accelerate connect_variable \ foo/ptr_in to \ my_memory_with_two_cycles_read_latency int foo(int *ptr_in, int x, int y, int z) { int ...
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... In other words, an inner loop translates to a state machine within a state machine. As the state machine for an inner loop executes, the outer state machine stalls until the inner loop has completed. Altera Corporation November 2009 Inner loop Subfunction call Memory transfer 9 ...
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... However, the state machine does not complete in three clock cycles, because State 1 consists of a sub-state-machine, which requires multiple clock cycles to complete. 3–40 Nios II C2H Compiler User Guide Figure 3–19 shows the dependency graph for 3–33. Figure 3–19, some part of the for loop depends on 9.1 Altera Corporation November 2009 ...
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... If the subfunction does not contain loops or shared data dependencies the C2H Compiler can pipeline the subfunction. For details about pipelined subfunctions, see Altera Corporation November 2009 C-to-Hardware Mapping Reference Example 3–34 has two while loops with no “ ...
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... Nios II C2H Compiler User Guide shows the dependency graph for the loop block in 3–35. 9.1 Altera Corporation November 2009 ...
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... Figure 3–20. Dependency Graph for a Loop Block Altera Corporation November 2009 C-to-Hardware Mapping Reference 9.1 Nios II C2H Compiler User Guide 3–43 ...
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... Nios II C2H Compiler User Guide illustrates how the C2H Compiler schedules successive Figure 3–20. The C2H Compiler is able to Dependencies”. 9.1 Altera Corporation November 2009 ...
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... State 2 in iteration (N-1). The arrow for data in State 0 illustrates the ideal case in which a state depends only on its own output. The ideal case does not restrict the scheduling of successive iterations. Altera Corporation November 2009 C-to-Hardware Mapping Reference shows the dependency graph for the do loop in 3– ...
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... Nios II C2H Compiler User Guide illustrates how the C2H Compiler schedules successive Figure 3–22, based on the restrictions to satisfy the loop-carried dependency. 3–23, the cyclic arrow for hash in “Read Operations with Latency” on page 9.1 Figure 3–22 translates to 3–37, Altera Corporation November 2009 ...
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... Connections” on page Example 3–37. Accessing Memory with Latency #pragma altera_accelerate connect_variable \ sum_elements/list to \ my_mem_with_two_cycles_read_latency int sum_elements (int *list, int len) { int i; ...
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... Nios II C2H Compiler User Guide Figure 3–24 remains empty because list has two cycles of read illustrates how the C2H Compiler schedules successive Figure 3–25, the C2H Compiler is able to start a new iteration 3–39). 9.1 Altera Corporation November 2009 ...
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... Data sets from multiple subfunction calls are pipelined in the subfunction’s state machine.The code in contains a subfunction which is pipelined by the C2H Compiler. Altera Corporation November 2009 3–39). Inner loops, subfunction calls, and slow memory accesses all 9.1 C-to-Hardware Mapping Reference “ ...
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... Scheduling Example 3–38. Pipelined Subfunction int MAX(int a, int b) { return ((a > b b); } #pragma altera_accelerate connect_variable MAX_loop/a to sdram #pragma altera_accelerate connect_variable MAX_loop/b to onchip_ram_64_kbytes int MAX_loop(int * _ _restrict_ _ a, int * __restrict__ b) { int for ( < 1024; i++) { c += MAX(a[i], b[i]); } return the subfunction performs a memory access that stalls, then the outer state machine also stalls ...
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... A resource only becomes shared Sharing under-utilized. In other words, the C2H Compiler only shares a resource if the performance of accelerator is not affected. resources that can be shared automatically by the C2H Compiler. Table 3–6. Sharable Resource Dereference or Description Operator *var Memory Access var[] * Multiply ...
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... Avalon-MM master port. The C2H Compiler only shares resources if they reside at the same level within a loop or function. shared and independent resources. 3–52 Nios II C2H Compiler User Guide Figure 3–26 shows an algorithm which contains 9.1 Altera Corporation November 2009 ...
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... With pipelined subfunctions, the latency overhead of this approach is not excessive. For further details, see page Altera Corporation November 2009 3–41. 9.1 C-to-Hardware Mapping Reference “ ...
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... Resource Sharing 3–54 Nios II C2H Compiler User Guide 9.1 Altera Corporation November 2009 ...
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... Introduction This chapter discusses the Altera Nios II C-to-Hardware Acceleration (C2H) Compiler view available in the Nios II IDE. Understanding the C2H view allows you to estimate the resource usage and the performance of the accelerator. You can use this information to perform optimizations to reduce the logic resource size or increase the performance of the accelerator ...
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... Analyze all accelerators lets you quickly display build information without regenerating the SOPC Builder system. This configuration does not overwrite the existing accelerator logic, it simply analyzes the source code. 4–2 Nios II C2H Compiler User Guide *summarizes the project build configurations. Meaning 9.1 Altera Corporation November 2009 ...
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... Each of these resources has information about how they are configured in the hardware and the line of source code that mapped to them. In the following discussion of these resources, refer to Altera Corporation November 2009 Meaning describes the available function build configurations. Avalon-MM master ports ...
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... Nios II processor, uncached pointers to the shared memory might result in spurious Avalon-MM transfers to addresses >= 0x80000000. 4–4 Nios II C2H Compiler User Guide Meaning Cache and Tightly-Coupled Memory (1) Handbook. Cache and Tightly-Coupled Memory to learn more about cache coherency. 9.1 chapter of the Nios II Software chapter of the Nios II Software Altera Corporation November 2009 ...
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... Example 4–1. Vector Power Calculation #pragma altera_accelerate connect_variable power_calculation/voltage to onchipRAM1 #pragma altera_accelerate connect_variable power_calculation/current to onchipRAM1 #pragma altera_accelerate connect_variable power_calculation/power to onchipRAM2 void power_calculation ( short * _ _restrict__ voltage, short * _ _restrict_ _ current, short * _ _restrict_ _ power, short downscale, int length) { int i; for < length; i++) { *power++ = (*voltage++ * *current++) >> downscale; ...
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... Avalon-MM resources by creating a single Avalon-MM master port to access memory for multiple dereference operations if there is no performance disadvantage. In voltage and current reside in the same single-ported physical 4–6 Nios II C2H Compiler User Guide Example 4–1, the data pointed to by 9.1 Altera Corporation November 2009 ...
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... For each dereference operation, the report shows the source line on which the C statement appears. It also shows the variable being dereferenced, and the data direction (read or write). Any one statement is either a read Altera Corporation November 2009 Example 4–1 the pointer power requires a 9 ...
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... Nios II C2H Compiler User Guide 4–5, the connection pragmas forced the C2H Optimizing Nios II C2H Compiler Results Chapter 3, C-to-Hardware Mapping illustrates the information presented in the C2H build report Example 4–1 on page 9.1 Reference, the data 4–5. Altera Corporation November 2009 ...
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... When the report does not show a pipeline value for a resource, that means that the operator is purely combinational, with no latency. Altera Corporation November 2009 The resource usage does not reflect the final resource utilization of the compiled hardware. When ANSI C code is compiled, small integer data types are promoted to the int data type. In Figure 4– ...
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... In the following discussion of information shown in the performance section, refer to Example 4–2. CRC32 (Ethernet CRC) #pragma altera_accelerate connect_variable\ crc_calculation/data to onchipRAM1 #pragma altera_accelerate connect_variable\ crc_calculation/table to onchipRAM2 unsigned long crc_calculation ( unsigned char * _ _ restrict_ _ data, unsigned long * _ _ restrict_ _ table, ...
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... Figure 4–4 path is identified by its starting and ending states. In will see, the critical path turns out to be states 6 through 11. The report identifies this path as 6--->11. Altera Corporation November 2009 Chapter 3, C-to-Hardware Mapping It is important to remember that if the accelerator re-enters the loop multiple times, it incurs the loop latency each time ...
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... The C2H Compiler displays one critical loop variable (crc way of identifying the critical path. 4–12 Nios II C2H Compiler User Guide 9.1 Figure 4–5. The Altera Corporation November 2009 ...
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... The report shows that the critical path is either 0--->6, or 6--->11. Since the C2H Compiler pipelines the logic contained in loops, multiple states are active concurrently. of Example 4–2 on page the critical path, the accelerator begins each execution of that statement as Altera Corporation November 2009 lut_addr=(crc&0xFF)^ lut_addr table [lut_addr]; ...
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... Nios II C2H Compiler User Guide 14:crc=((crc>>8)^ table[lut_addr]; State(6 11) *data++; State(0 6) 14:crc=((crc>>8)^ table[lut_addr]; State(6 13:lut_addr=((crc&0xFF)^ *data++; State(0 9 11) 6) 14:crc=((crc>>8)^ table[lut_addr]; State(6 11) 13:lut_addr=((crc&0xFF)^ *data++; State(0 6) Altera Corporation November 2009 24 ...
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... Figure 4–7. CRC Scheduling Per Assignment Using the methodology from create a chart such as page Altera Corporation November 2009 4–2, there are four assignments in the loop. This section “Cycles Per Loop Iteration Figure 4–8, corresponding to 4– ...
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... State(6 11) 12:i++; 1) 12:i< length; State(1 2) *data++; State(0 6) 14:crc=((crc>>8)^table [lut_addr]; State(6 12:i++; State(0 1) 12:i< length; State(1 2) 13:lut_addr=((crc&0xFF)^ *data++; State(0 9 11) 6) 14:crc=((crc>>8)^table [lut_addr]; State(6 11) Altera Corporation November 2009 ...
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... When the states are mapped and presented in this section of the C2H build report, as shown in Figure 4–9. CRC Scheduling Per State Altera Corporation November 2009 Figure 4–9. 9.1 Nios II C2H Compiler User Guide Understanding the C2H View Example 4– ...
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... CPLI crc=(crc>>8)^table[lut_addr]; (State 10) crc=(crc>>8)^table[lut_addr]; (State 11) crc=(crc>>8)^table[lut_addr]; 9.1 CPLI Altera Corporation November 2009 ...
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... Further Reading For more advice on using the information presented in the C2H view, refer to the Embedded Design Handbook. Altera Corporation November 2009 Example 4–2, a total of 12 states is required to schedule the Figure 4–10 outlines the same information presented in Optimizing Nios II C2H Compiler Results 9 ...
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... Further Reading 4–20 Nios II C2H Compiler User Guide 9.1 Altera Corporation November 2009 ...
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... Nios II Software Build Tools Command Line C2H Compiler projects created on the command line cannot be imported into the Nios II Software Build Tools for Eclipse. Altera recommends creating new C2H accelerators with the Nios II IDE. nios2-c2h-generate-makefile \ --sopcinfo=<SOPC Builder System File> [OPTIONS] This command creates a new c2h ...
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... These rules in turn include the c2h.mk fragment generated by this command. f For more information about nios2-app-generate-makefile, refer to the Nios II Software Build Tools Reference the Nios II Software Developer’s 9.1 Meaning option. Defaults to 0. Nios II Nios II Software Developer’s chapter of Handbook. Altera Corporation November 2009 ...
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... The report is saved as an XML file in the application directory. The name of the report file is <function_name>.prop, where <function_name> is the name of the accelerated function. For details of the report’s contents, refer to “Performance” on page 4–10 Altera Corporation November 2009 “Resources” on page 4–3 of Chapter 4, Understanding the C2H 9 ...
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... C2H Performance Metrics 5–4 Nios II C2H Compiler User Guide 9.1 Altera Corporation November 2009 ...
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... If you use the connection pragma for a specific variable, the C2H Compiler connects only the slave ports specified in pragma statements. Altera Corporation November 2009 6. Pragma Reference #pragma altera_accelerate connect_variable \ <function name>/<variable name> <module>[/<slave name>] [arbitration_share <shares>] 9.1 6–1 ...
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... Example 6–2 variable's master ports to multiple slave ports. Example 6–2. Pragma Connecting a Master Ports to Multiple Slave Ports #pragma altera_accelerate connect_variable foo/my_ptr to onchip_buffer_0 #pragma altera_accelerate connect_variable foo/my_ptr to ext_ram_bridge #pragma altera_accelerate connect_variable foo/my_ptr to sdram #pragma altera_accelerate connect_variable \ int foo(int *my_ptr) { int x = *my_ptr; my_ptr[8] = 23; ...
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... Example 6–3 module named sdram with an arbitration share of 16. Example 6–3. Pragma Specifying Arbitration Share #pragma altera_accelerate connect_variable myfunc/x to sdram \ arbitration_share 16 Flow Control Avalon-MM transfers with flow control force a master port to obey flow control signals controlled by a slave port ...
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... ACCELERATOR Check status ACCELERATOR 6–4 Nios II C2H Compiler User Guide #pragma altera_accelerate \ enable_interrupt_for_function <function name> The accelerator's control slave has an IRQ signal, which is asserted every time the function has completed execution. The polling loop in the generated driver file is removed. When the function is called, the CPU immediately returns after launching the accelerator ...
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... By default, the C2H compiler will attempt to share a single master between ptr_a and ptr_b, preventing these dereference operations from being scheduled concurrently and possibly degrading performance. Altera Corporation November 2009 Exception Handling chapter of the for more information about creating interrupt service routines. “ ...
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... Unshare Pointer Pragma Example 6–5. Automatically Shared Master Port #pragma altera_accelerate connect_variable ptr_a to onchip_memory_0 #pragma altera_accelerate connect_variable ptr_a to onchip_memory_1 #pragma altera_accelerate connect_variable ptr_b to onchip_memory_0 #pragma altera_accelerate connect_variable ptr_b to onchip_memory_1 if (x) { ptr_a = ONCHIP_MEMORY_1_BASE; ptr_b = ONCHIP_MEMORY_2_BASE; } else { ptr_a = ONCHIP_MEMORY_2_BASE; ptr_b = ONCHIP_MEMORY_1_BASE ... perform some dereference operations with ptr_a and ptr_b ... */ ...
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... The following types are not supported by the C2H Compiler: ■ ■ ■ ■ ■ The following types are supported if specific conditions are met: ■ Altera Corporation November 2009 7. ANSI C Compliance and float - section 6.3.1.5 double - section 6.3.1.5 _Complex – section 6.3.1.7 _Bool – section 6.3.1.2 _Imaginary – section 6.3.1.7 Floating constants are supported only after casting to a supported type ...
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... The C2H Compiler does not support the initialization statement which concatenates two strings, such as the following: char s[] = "this" " string"; The following declaration is supported: char s[] = "this string"; struct my_struct { unsigned int tbits:3; } ms; ms.tbits = 0xFF; struct my_struct { unsigned int tbits; } ms; ms.tbits = 0xFF & 7; 9.1 Altera Corporation November 2009 ...
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... Expressions The C2H Compiler does not support the following C operators. Unary Operator (Address Operator) (Section 6.5.3.2, Paragraph 1) The unary & operator used as an address operator is not supported. Altera Corporation November 2009 int a[] = {[5]=2}; int a[6]; /* establish array size */ a[5]=2; /* assign element 5 */ int a[6]={0,0,0,0,0,2} ...
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... Nios II C2H Compiler User Guide void foo() { int a=0; int c=analyze(&a); } int analyze( int * p ); int *pa = &a; int foo() { return analyze(pa); } int analyze( int * (i-- || j--) int 9.1 Altera Corporation November 2009 ...
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... Function Pointers (Section 6.7.5.3, Paragraph 8) Function pointers are supported if used to point to functions that exist inside the hardware accelerator. The C2H Compiler does not support function pointers used as input or output arguments to an accelerator. Altera Corporation November 2009 int my_func(int (*)(), double (*)[3]); int my_func(int (*)(char *), double (*)[]); ...
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... The following function declaration which defines the argument types inside the function argument list is supported: 7–6 Nios II C2H Compiler User Guide defines three sub-functions, sub_plus_one(), void foo(a,b,c); void foo(char a, char b, char c); 9.1 Altera Corporation November 2009 ...
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... You can replace recursive functions with equivalent code that implements the function without using recursion. equivalent implementation of the factorial function without using recursion. Altera Corporation November 2009 void doDMA(int a) { void analyze(int i); ... } void analyze(int i); void doDMA(int a) { ...
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... The use of trigraph sequences to reduce the standard C character set to the smaller ISO 646 character set is not supported. The following function call uses unsupported trigraph “??<“ in place of “{“: 7–8 Nios II C2H Compiler User Guide int cmpchar(char *c2) 9.1 Altera Corporation November 2009 ...
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... The C2H Compiler does not support external subfunctions. You must locate the subfunction in the same source file as the accelerated function. Restrictions This is because, unlike the #include construct external function reference requires the presence of a linker. The C2H Compiler has no linker. Altera Corporation November 2009 { char *c1 = "??<"; return (c1!=c2); } ...
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... Other Restrictions 7–10 Nios II C2H Compiler User Guide 9.1 Altera Corporation November 2009 ...
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... Altera Corporation Additional Information Quartus II Handbook, volume 4: SOPC Builder Overview chapter of the Nios II Software Developer's Handbook Cache and Tightly-Coupled Memory Developer's Handbook Exception Handling chapter of the Handbook Using the Nios II Integrated Development Environment ...
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... Extended resource sharing. ● Support for the software build tools. ● Interrupt generation. Additional chapter on Nios II software build tools Additional chapter on pragmas Move from chapter 5 to chapter 7 Additional chapter on C2H view Move from chapter 4 to chapter 5 First publication 9.1 Altera Corporation ...
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... The hand points to information that requires special attention. Altera Corporation Information Type You can also contact your local Altera sales office or sales representative. Meaning , \qdesigns directory, d: drive, chiptrip.gdf file. MAX , Active-low signals are denoted by suffix input. . Also, references to C code are shown in Courier. ...
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... A warning calls attention to a condition or possible situation that can cause injury w to the user. r The angled arrow indicates you should press the Enter key. f The feet direct you to more information on a particular topic. 4 Nios II C2H Compiler User Guide Meaning 9.1 Altera Corporation ...