IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 87

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Example 3–37. Accessing Memory with Latency
#pragma altera_accelerate connect_variable \
int sum_elements (int *list, int len)
{
}
Altera Corporation
November 2009
int i;
int sum = 0;
for (i=0; i<len; i++)
sum_elements/list to \
my_mem_with_two_cycles_read_latency
sum += *list++;
that performs Avalon-MM pipelined read transfers. Inside the
accelerator, the master port connects to a FIFO, which guarantees the
accelerator can receive data for all pending read transfers, regardless of
whether the state machine stalls.
Figure 3–24
demonstrates a loop that pipelines memory accesses with latency. This
example uses the connection pragma to connect the master port for
variable list to a slave memory named
my_mem_with_two_cycles_read_latency, as described in section
“Master-Slave Connections” on page
Figure 3–24. Accessing Memory with Latency
shows the dependency graph for
9.1
3–23.
C-to-Hardware Mapping Reference
Nios II C2H Compiler User Guide
Example
3–37, which
3–47