IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 102

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Resources
4–8
Nios II C2H Compiler User Guide
f
or a write. However, when an Avalon-MM master port is shared among
two or more dereference statements, it might need to support both
directions.
In
Compiler to create a single, shared Avalon-MM master port called
Master Resource 0. If the connection pragmas were omitted from the
example software, all dereference operations would have resulted in a
single Avalon-MM master port resource connecting to all Avalon-MM
memory slave ports.
For more information about connection pragmas, refer to “Optimizing
Memory Connections” in the
chapter of the Embedded Design Handbook.
Mathematical Operator Resources
As mentioned in
types used in the C code determine the width of the logic which the C2H
Compiler generates. The resources section of the C2H build report shows
the width of all the resources listed. The resources section also shows the
degree of pipelining on each operator resource. This information helps
you understand the accelerator scheduling information shown in the
Performance section.
Figure 4–3
for mathematical operator resources in
Example 4–1 on page
illustrates the information presented in the C2H build report
Chapter 3, C-to-Hardware Mapping
9.1
4–5, the connection pragmas forced the C2H
Optimizing Nios II C2H Compiler Results
Example 4–1 on page
Reference, the data
Altera Corporation
November 2009
4–5.