IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 62

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Memory Accesses
Figure 3–10. Data Generation for a Write Operation
3–22
Nios II C2H Compiler User Guide
port. After some number of clock cycles determined by the slave memory
latency and arbitration delay, valid readdata returns to the master port.
(See section
Data Computation
For write operations to dereferenced pointers, data-computation logic in
the accelerator computes the value of the expression to write to memory.
This value is the write-data for an Avalon-MM master transfer to
memory. Data-computation logic operates in parallel with the address-
computation logic.
Consider the pointer dereference in the following code which performs a
write operation:
*(ptr_to_int + i) = x + y;
Figure 3–10
dereference for a write operation.
shows an example of the logic created for this pointer
“Read Operations with Latency” on page
9.1
3–37.)
Altera Corporation
November 2009