E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 453

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Port G Data Register (PGDR)
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PGDR is initialized to H'E0 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Bit
Initial value
R/W
Modes 1 and 2
Pin PG
to 1, and as an input port when the bit is cleared to 0.
For pins PG
while clearing the bit to 0 makes the pin an input port.
Modes 3 and 7
Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing
the bit to 0 makes the pin an input port.
Modes 4 to 6
Pins PG
PGDDR bits are set to 1, and as input ports when the bits are cleared to 0.
Pin PG
output pin when PSRAM interface is designated. Otherwise, setting the corresponding
PGDDR bit to 1 makes the pin an output port, while clearing the bit to 0 makes the pin an
input port.
For details of the DRAM and PSRAM interfaces, see section 6, Bus Controller.
4
0
4
functions as a bus control output pin (CS
functions as the CAS output pin when DRAM interface is designated, and as the OE
to PG
:
:
:
3
to PG
1
function as bus control output pins (CS
—
—
7
1
0
, setting the corresponding PGDDR bit to 1 makes the pin an output port,
—
—
6
1
—
—
5
1
PG4DR
R/W
4
0
0
) when the corresponding PGDDR bit is set
Rev. 5.00 Sep 14, 2006 page 423 of 1060
PG3DR
0
R/W
to CS
3
0
3
) when the corresponding
PG2DR
R/W
2
0
PG1DR
Section 9 I/O Ports
REJ09B0331-0500
R/W
1
0
PG0DR
4
R/W
to PG
0
0
0
).