E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 20

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.3
7.4
7.5
7.6
7.7
Section 8 Data Transfer Controller
8.1
8.2
Rev. 5.00 Sep 14, 2006 page xviii of xxviii
7.2.5
Register Descriptions (2) (Full Address Mode) ................................................................ 237
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Register Descriptions (3) .................................................................................................. 250
7.4.1
7.4.2
7.4.3
Operation .......................................................................................................................... 255
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 DMAC Bus Cycles (Dual Address Mode)........................................................... 284
7.5.11 DMAC Bus Cycles (Single Address Mode) ........................................................ 292
7.5.12 Write Data Buffer Function ................................................................................. 298
7.5.13 DMAC Multi-Channel Operation ........................................................................ 299
7.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC,
7.5.15 NMI Interrupts and DMAC.................................................................................. 301
7.5.16 Forced Termination of DMAC Operation............................................................ 302
7.5.17 Clearing Full Address Mode ................................................................................ 303
Interrupts ........................................................................................................................... 304
Usage Notes ...................................................................................................................... 305
Overview........................................................................................................................... 309
8.1.1
8.1.2
8.1.3
Register Descriptions ........................................................................................................ 312
8.2.1
8.2.2
DMA Band Control Register (DMABCR)........................................................... 231
Memory Address Register (MAR)....................................................................... 237
I/O Address Register (IOAR) .............................................................................. 238
Execute Transfer Count Register (ETCR) ........................................................... 238
DMA Control Register (DMACR)....................................................................... 240
DMA Band Control Register (DMABCR)........................................................... 244
DMA Write Enable Register (DMAWER) .......................................................... 250
DMA Terminal Control Register (DMATCR)..................................................... 253
Module Stop Control Register (MSTPCR) .......................................................... 254
Transfer Modes .................................................................................................... 255
Sequential Mode .................................................................................................. 258
Idle Mode............................................................................................................. 261
Repeat Mode ........................................................................................................ 264
Single Address Mode........................................................................................... 268
Normal Mode....................................................................................................... 271
Block Transfer Mode ........................................................................................... 274
DMAC Activation Sources .................................................................................. 280
Basic DMAC Bus Cycles..................................................................................... 283
and the DMAC..................................................................................................... 300
Features................................................................................................................ 309
Block Diagram ..................................................................................................... 310
Register Configuration......................................................................................... 311
DTC Mode Register A (MRA) ............................................................................ 312
DTC Mode Register B (MRB)............................................................................. 314
................................................................................. 309