E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 104

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E62655RUSB

Manufacturer Part Number
E62655RUSB
Description
EMULATOR BASE H8S/2655R W/USB
Manufacturer
Renesas Electronics America
Type
Microcontrollerr
Datasheet

Specifications of E62655RUSB

Contents
E6000 Emulator Unit and 4 Logic Probes
For Use With/related Products
H8S/2655R
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Section 3 MCU Operating Modes
Bit 7
MACS
0
1
Bit 6—Reserved: Read-only bit, always read as 0.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.
Bit 5
INTM1
0
1
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG
0
1
Bits 2 and 1—Reserved: Read-only bits, always read as 0.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset status is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Rev. 5.00 Sep 14, 2006 page 74 of 1060
REJ09B0331-0500
Description
Non-saturating calculation for MAC instruction
Saturating calculation for MAC instruction
Bit 4
INTM0
0
1
0
1
Description
An interrupt is requested at the falling edge of NMI input
An interrupt is requested at the rising edge of NMI input
Description
On-chip RAM is disabled
On-chip RAM is enabled
Interrupt
Control Mode
0
1
2
3
Description
Control of interrupts by I bit
Control of interrupts by I bit, U bit, and ICR
Control of interrupts by I2 to I0 bits and IPR
Control of interrupts by I, UI, and I2 to I0 bits,
and ICR and IPR
(Initial value)
(Initial value)
(Initial value)
(Initial value)

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