E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 329

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

When the write data buffer function is activated, the DMAC recognizes that the bus cycle
concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one
state after the start of the DMA write cycle or single address transfer.
7.5.13
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table
7.13 summarizes the priority order for DMAC channels.
Table 7.13 DMAC Channel Priority Order
Short Address Mode
Channel 0A
Channel 0B
Channel 1A
Channel 1B
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.13.
Figure 7.34 Example of Single Address Transfer Using Write Data Buffer Function
Internal read signal
External address
Internal address
DMAC Multi-Channel Operation
DACK
RD
DMA
read
Full Address Mode
Channel 0
Channel 1
DMA
single
CPU
read
Rev. 5.00 Sep 14, 2006 page 299 of 1060
DMA
single
Priority
High
Low
Section 7 DMA Controller
CPU
read
REJ09B0331-0500