HS7046EPH60H Renesas Electronics America, HS7046EPH60H Datasheet - Page 224

• Manufacturer Part Number: HS7046EPH60H
• Description: DEV EMULATOR BASE SH7046
• Manufacturer: Renesas Electronics America
• Series: SuperH®r
• Type: Microcontrollerr

Specifications of HS7046EPH60H

• Contents: E6000 Emulator and CD-ROM
• For Use With/related Products: SH7046
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.5.3
• A break will occur several cycles after a condition is satisfied.
• The address bus and data bus conditions are satisfied on the bus cycles where the values on the address bus
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or data bus match. Consider the following points when setting these conditions.
⎯ 32-bit bus area
⎯ 16-bit bus area
⎯ 8-bit bus area
• Longword access
• Word access
• Byte access
• Longword access
• Word access
• Byte access
All accesses are done in bytes in this area (a longword is accessed in four byte cycles, and a word in two
byte cycles). Any address condition, whether an even or odd address, is valid. A data condition is only
valid when specified as byte.
On-Emulator Break
Longword data is read and written in a single bus cycle. A data condition is only valid for a longword
access when specified as longword. An address condition is only valid for a longword access when
specified as a multiple of four.
Word data is read and written in a single bus cycle. A data condition is only valid for a word access
when specified as word. An address condition is only valid for a word access when specified as a
multiple of two.
Byte data is read and written in a single bus cycle. A data condition is only valid for a byte access
when specified as byte. Any address condition, whether an even or odd address, is valid.
Longword data is read and written in two bus cycles. A data condition is only valid for a longword
access when specified as word. An address condition is only valid for a longword access when
specified as a multiple of two.
Word data is read and written in a single bus cycle. A data condition is only valid for a word access
when specified as word. Any multiple of two is a valid address condition.
Byte data is read and written in a single bus cycle. A data condition is only valid for a byte access
when specified as byte. Any address condition, whether an even or odd address, is valid.