DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 24

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 2: Xilinx Silicon Solutions
14
CoolRunner-II Architecture Description
CoolRunner-II Function Block
The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. The
underlying architecture is a traditional CPLD architecture, combining macrocells into
function blocks interconnected with a global routing matrix, the Xilinx Advanced
Interconnect Matrix (AIM). The function blocks use a PLA configuration that allows all
product terms to be routed and shared among any of the macrocells of the function block.
Design software can efficiently synthesize and optimize logic that is subsequently fit to the
function blocks and connected with the ability to utilize a very high percentage of device
resources. The software easily and automatically manages design changes, exploiting the
100% routeability of the PLA within each function block. This extremely robust building
block delivers the industry’s highest pin-out retention under very broad design conditions.
The design software automatically manages device resources so that you can express your
designs using completely generic constructs, without needing to know the architectural
details. If you’re more experienced, you can take advantage of these details to more
thoroughly understand the software’s choices and direct its results.
Figure 2-5
interconnect to each other within the internal interconnect matrix. Each function block
contains 16 macrocells.
The CoolRunner-II CPLD function blocks contain 16 macrocells, with 40 entry sites for
signals to arrive for logic creation and connection. The internal logic engine is a 56-product
term PLA. All function blocks, regardless of the number contained in the device, are
identical. At the high level, the p-terms reside in a PLA. This structure is extremely flexible
and very robust when compared to fixed or cascaded p-term function blocks. Classic
CPLDs typically have a few p-terms available for a high-speed path to a given macrocell.
They rely on capturing unused p-terms from neighboring macrocells to expand their
product term tally when needed. The result of this architecture is a variable timing model
and the possibility of stranding unusable logic within the function block.
I/O Pin
I/O Pin
I/O Pin
JTAG
shows the high-level architecture whereby function blocks attach to pins and
BSC and ISP
16
16
Figure 2-5: CoolRunner-II High-Level Architecture
MC16
MC1
MC2
Direct Inputs
www.xilinx.com
Function
Block 1
PLA
16 FB
40
Clock and Control Signals
BSC Path
AIM
16 FB
40
Function
Block n
PLA
Direct Inputs
Programmable Logic Design
MC16
MC1
MC2
16
16
June 12, 2006
DS090_01_121201
I/O Pin
I/O Pin
I/O Pin
R