DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 137

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Programmable Logic Design
June 12, 2006
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EPLD – Erasable Programmable Logic Devices, synonymous with CPLDs. PAL-derived
programmable logic devices that implement logic as sum-of- products driving macrocells.
EPLDs are known to have short pin-to-pin delays, and can accept wide inputs, but have
relatively high power consumption and fewer flip-flops than FPGAs.
Embedded RAM – Read-write memory stored inside a logic device. Avoids the delay and
additional connections of an external RAM.
ESD – Electro-Static Discharge. High-voltage discharge can rupture the input transistor
gate oxide. ESD-protection diodes divert the current to the supply leads.
5-Volt Tolerant – Characteristic of the input or I/O pin of a 3.3V device that allows this pin
to be driven to 5V without any excessive input current or device breakdown. Very desirable
feature.
FIFO – First-In-First-Out memory, where data is stored in the incoming sequence and is
read out in the same sequence. Input and output can be asynchronous to each other. A
FIFO needs no external addresses, although all modern FIFOs are implemented internally
with RAMs driven by circular read and write counters.
FIT – Failure In Time. Describes the number of device failures statistically expected for a
certain number of device-hours. Expressed as failures per one billion device hours. Device
temperature must be specified. MTBF can be calculated from FIT.
Flash – Non-volatile programmable technology, an alternative to Electrically-Erasable
Programmable Read-Only Memory (EEPROM) technology. The memory content can be
erased by an electrical signal. This allows in-system programmability and eliminates the
need for ultraviolet light and quartz windows in the package.
Flip-Flop – Single-bit storage cell that samples its Data input at the active (rising or falling)
clock edge, and then presents the new state on its Q output after that clock edge, holding
it there until after the next active clock edge.
Floorplanning – Method of manually assigning specific parts of the design to specific chip
locations. Can achieve faster compilation, better utilization, and higher performance.
Footprint – The printed circuit pattern that accepts a device and connects its pins
appropriately. Footprint-compatible devices can be interchanged without modifying the PC
board.
FPGA – Field Programmable Gate Array. An integrated circuit that contains configurable
(programmable) logic blocks and configurable (programmable) interconnect between
those blocks.
Function Generator – Also called look-up-table, with N-inputs and one output. Can
implement any logic function of its N-inputs. N is between 2 and 6; 4-input function
generators are most popular.
GAL – Generic Array Logic. Lattice name for a variation on PALs Gate. Smallest logic
element with several inputs and one output. AND gate output is high when all inputs are
high. OR gate output is high when at least one input is high. A 2-input NAND gate is used
as the measurement unit for gate array complexity.
Gate Array – ASIC where transistors are pre-defined, and only the interconnect pattern is
customized for the individual application.
GTL – Gunning Transceiver Logic. A high-speed, low-power back-plane standard.
GUI – Graphic User Interface. A way of representing the computer output on the screen as
graphics, pictures, icons, and windows. Pioneered by Xerox and the Macintosh, now
universally adopted (e.g., by Windows 95).
www.xilinx.com
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