DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 123

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Programming
Programmable Logic Design
June 12, 2006
R
To program a Spartan-3:
1.
2.
3.
4.
5.
Note:
Programmer. Ensure that the cable is plugged in to the computer and that the ribbon cable/flying
leads are connected properly to the board. You must also connect the power jack of the Parallel-IV
cable to either the mouse or keyboard port of the PC.
6.
Right-click on Generate Programming File and click on Properties.
Under the Start-Up Options category, ensure that the FPGA Start-Up Clock is
set to JTAG Clock by selecting JTAG Clock from the drop-down menu. Click OK
Double-click on Generate Programming File.
This operation creates a .bit file that can be used by the iMPACT programmer to
configure a device.
Expand the Generate Programming File tools subsection.
Double-click on Configure Device (iMPACT).
If the chain specified in the design is not automatically picked up from the ISE tool,
right-click in the top half of the iMPACT window and select Add Xilinx Device.
A DLC7 Parallel-IV JTAG cable is required to configure the device from the iMPACT
www.xilinx.com
Figure 6-15: JTAG Clock Selection
Programming
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