DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 119

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Programmable Logic Design
June 12, 2006
R
7.
8.
9.
The Constraints Editor is invoked and picks up the LOC constraints entered in
PACE. These can be edited by double-clicking on them in the read-write window or
under the Ports tab in the Main window.
With the Global tab selected right-click on the Period entry for the Clock signal. The
Clock Period dialog box will appear. Enter a period of 10 ns. as shown in
Click OK.
Click on the Ports tab in the Constraints Editor. As there were already constraints in
the UCF, they have been imported.
Figure 6-9: Specify Period Constraint
www.xilinx.com
The Constraints File
Figure
6-9.
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