DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 103

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Programmable Logic Design
June 12, 2006
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10. The Constraints Editor recognizes the one global signal in the design. Double-
11. In the Clock Period definition window, change the Time value to 10 ns. The duty
12. Click OK. The period constraint is now written into the UCF file and can be seen in the
13. Click the Ports tab in the Constraints Editor. As there were already constraints
click in the Period window of the global clock signal.
cycle should stay at 50% high, 50% low.
constraints list at the bottom of the Constraints Editor. A period constraint
ensures that the internal paths starting and ending at synchronous points (flip-flop,
latch) have a logic delay less than 10 ns.
in the UCF, they have been imported.
Figure 5-9: Clock Period Editor Window
www.xilinx.com
Constraints Editor
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