DK-DEV-2AGX260N Altera, DK-DEV-2AGX260N Datasheet - Page 41

• Manufacturer Part Number: DK-DEV-2AGX260N
• Description: KIT DEV FPGA 2AGX260 W/6.375G TX
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX260N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2696

Chapter 2: Board Components
Components and Interfaces
Table 2–36. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
© July 2010 Altera Corporation
Reference
J2.101
J2.102
Board
J2.47
J2.48
J2.49
J2.50
J2.53
J2.54
J2.55
J2.56
J2.59
J2.60
J2.61
J2.62
J2.65
J2.66
J2.67
J2.68
J2.71
J2.72
J2.73
J2.74
J2.77
J2.78
J2.79
J2.80
J2.83
J2.84
J2.85
J2.86
J2.89
J2.90
J2.91
J2.92
J2.95
J2.96
J2.97
J2.98
LVDS TX bit 0 or CMOS bit 4
LVDS RX bit 0 or CMOS bit 5
LVDS TX bit 0n or CMOS bit 6
LVDS RX bit 0n or CMOS bit 7
LVDS TX bit 1 or CMOS bit 8
LVDS RX bit 1 or CMOS bit 9
LVDS TX bit 1n or CMOS bit 10
LVDS RX bit 1n or CMOS bit 11
LVDS TX bit 2 or CMOS bit 12
LVDS RX bit 2 or CMOS bit 13
LVDS TX bit 2n or CMOS bit 14
LVDS RX bit 2n or CMOS bit 15
LVDS TX bit 3 or CMOS bit 16
LVDS RX bit 3 or CMOS bit 17
LVDS TX bit 3n or CMOS bit 18
LVDS RX bit 3n or CMOS bit 19
LVDS TX bit 4 or CMOS bit 20
LVDS RX bit 4 or CMOS bit 21
LVDS TX bit 4n or CMOS bit 22
LVDS RX bit 4n or CMOS bit 23
LVDS TX bit 5 or CMOS bit 24
LVDS RX bit 5 or CMOS bit 25
LVDS TX bit 5n or CMOS bit 26
LVDS RX bit 5n or CMOS bit 27
LVDS TX bit 6 or CMOS bit 28
LVDS RX bit 6 or CMOS bit 29
LVDS TX bit 6n or CMOS bit 30
LVDS RX bit 6n or CMOS bit 31
LVDS TX bit 7 or CMOS bit 32
LVDS RX bit 7 or CMOS bit 33
LVDS TX bit 7n or CMOS bit 34
LVDS RX bit 7n or CMOS bit 35
LVDS or CMOS clock out 1 or CMOS bit 36 HSMA_CLKOUT_P1
LVDS or CMOS clock in 1 or CMOS bit 37
LVDS or CMOS clock out 1 or CMOS bit 38 HSMA_CLKOUT_N1
LVDS or CMOS clock in 1 or CMOS bit 39
LVDS TX bit 8 or CMOS bit 40
LVDS RX bit 8 or CMOS bit 41
Description
HSMA_TX_D_P0
HSMA_RX_D_P0
HSMA_TX_D_N0
HSMA_RX_D_N0
HSMA_TX_D_P1
HSMA_RX_D_P1
HSMA_TX_D_N1
HSMA_RX_D_N1
HSMA_TX_D_P2
HSMA_RX_D_P2
HSMA_TX_D_N2
HSMA_RX_D_N2
HSMA_TX_D_P3
HSMA_RX_D_P3
HSMA_TX_D_N3
HSMA_RX_D_N3
HSMA_TX_D_P4
HSMA_RX_D_P4
HSMA_TX_D_N4
HSMA_RX_D_N4
HSMA_TX_D_P5
HSMA_RX_D_P5
HSMA_TX_D_N5
HSMA_RX_D_N5
HSMA_TX_D_P6
HSMA_RX_D_P6
HSMA_TX_D_N6
HSMA_RX_D_N6
HSMA_TX_D_P7
HSMA_RX_D_P7
HSMA_TX_D_N7
HSMA_RX_D_N7
HSMA_CLKIN_P1
HSMA_CLKIN_N1
HSMA_TX_D_P8
HSMA_RX_D_P8
Schematic Signal
Arria II GX FPGA Development Board, 6G Edition Reference Manual
Name
LVDS or 2.5-V
I/O Standard
Pin Number
Arria II GX
Device
AA10
AB10
AC5
AA9
AC4
AH2
AH1
AG1
AB9
AC1
AD1
AB2
AB1
AD4
AA1
AD7
AD6
AA7
Y11
AE4
Y10
AF4
AF1
AE2
AE1
AF3
AF2
AE3
W1
U6
U5
Y8
Y7
Y1
V4
Y2
V3
V2
2–33