DK-DEV-2AGX260N Altera, DK-DEV-2AGX260N Datasheet - Page 37

• Manufacturer Part Number: DK-DEV-2AGX260N
• Description: KIT DEV FPGA 2AGX260 W/6.375G TX
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX260N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2696

Chapter 2: Board Components
Components and Interfaces
Table 2–33. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
© July 2010 Altera Corporation
Board Reference
J14.B37
J14.B38
J14.B41
J14.B42
J14.B45
J14.B46
J14.A16
J14.A17
J14.A21
J14.A22
J14.A25
J14.A26
J14.A29
J14.A30
J14.A35
J14.A36
J14.A39
J14.A40
J14.A43
J14.A44
J14.A47
J14.A48
J14.A13
J14.A14
J14.A11
J14.B11
J14.B5
J14.B6
—
—
—
Add-in card receive bus
Add-in card receive bus
Add-in card receive bus
Add-in card receive bus
Add-in card receive bus
Add-in card receive bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Add-in card transmit bus
Motherboard reference clock
Motherboard reference clock
Reset
Wake signal
SMB clock
SMB data
x1 Presence detect
x4 Presence detect
x8 Presence detect
Description
PCIE_RX_P5
PCIE_RX_N5
PCIE_RX_P6
PCIE_RX_N6
PCIE_RX_P7
PCIE_RX_N7
PCIE_TX_P0
PCIE_TX_N0
PCIE_TX_P1
PCIE_TX_N1
PCIE_TX_P2
PCIE_TX_N2
PCIE_TX_P3
PCIE_TX_N3
PCIE_TX_P4
PCIE_TX_N4
PCIE_TX_P5
PCIE_TX_N5
PCIE_TX_P6
PCIE_TX_N6
PCIE_TX_P7
PCIE_TX_N7
PCIE_REFCLK_P
PCIE_REFCLK_N
PCIE_PERSTn
PCIE_WAKEn
PCIE_SMBCLK
PCIE_SMBDAT
PCIE_LED_X1
PCIE_LED_X4
PCIE_LED_X8
Schematic Signal
Name
Arria II GX FPGA Development Board, 6G Edition Reference Manual
I/O Standard
1.5-V PCML
LVTTL
HCSL
Arria II GX Device
Pin Number
AM31
AM32
AC33
AC34
AA33
AA34
AK31
AK32
AH31
AH32
AD31
AD32
AB31
AB32
AF31
AF32
AE29
AE30
W33
W34
M18
D27
D26
Y31
Y32
V31
V32
C30
C28
C27
N1
2–29