DK-DEV-2AGX260N Altera, DK-DEV-2AGX260N Datasheet - Page 16

• Manufacturer Part Number: DK-DEV-2AGX260N
• Description: KIT DEV FPGA 2AGX260 W/6.375G TX
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX260N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2696

2–8
Table 2–6. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 5)
Arria II GX FPGA Development Board, 6G Edition Reference Manual
Schematic Signal Name
fpga_config_d[0]
fpga_config_d[1]
fpga_config_d[2]
fpga_config_d[3]
fpga_config_d[4]
fpga_config_d[5]
fpga_config_d[6]
fpga_config_d[7]
flash_rdy_bsyn
fpga_conf_done
csense_adc_f0
csense_csn[0]
csense_csn[1]
factory_user
flash_resetn
fpga_nconfig
fpga_nstatus
clk2_os[0]
clk2_os[1]
clk2_pr[0]
clk2_pr[1]
csense_sck
csense_sdi
csense_sdo
flash_advn
clk2_rstn
flash_cen
flash_clk
flash_oen
flash_wen
fpga_dclk
ddr2_scl
ddr2_sda
fsm_a[0]
ep_clk
ep_cs
ep_di
ep_do
I/O Standard
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
2.5-V
Pin Number
EPM2210
M15
M16
P15
P14
N15
G16
H15
H16
H14
H13
K15
K16
D15
J14
J15
J16
L13
F15
M7
M6
C8
C9
D8
D7
B1
A4
A7
B4
B5
A6
A5
B6
H4
H3
A2
E7
J1
J2
EP2AGX125
Pin Number
AD28
AE25
AC26
M21
N26
L25
M3
M4
N4
R3
N3
N6
G2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T4
K5
C7
P6
L4
K3
K2
Programmable oscillator 2 output select 0
Programmable oscillator 2 output select 1
Programmable oscillator 2 prescaler 0
Programmable oscillator 2 prescaler 1
Programmable oscillator 2 reset
Power monitor frequency
Power monitor 0 chip select
Power monitor 1 chip select
Power monitor serial peripheral interface (SPI)
clock
Power monitor SPI data in
Power monitor SPI data out
DDR2 SODIMM EEPROM clock
DDR2 SODIMM EEPROM data
EEPROM clock
EEPROM chip select
EEPROM data in
EEPROM data out
Load factory or user design at power-up
FSM bus flash memory address valid
FSM bus flash memory chip enable
FSM bus flash memory clock
FSM bus flash memory output enable
FSM bus flash memory ready
FSM bus flash memory reset
FSM bus flash memory write enable
FPGA configuration done
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration data
FPGA configuration clock
FPGA configuration active
FPGA configuration ready
FSM bus address
MAX II CPLD EPM2210 System Controller
Description
© July 2010 Altera Corporation
Chapter 2: Board Components