DK-DEV-2AGX260N Altera, DK-DEV-2AGX260N Datasheet - Page 30

• Manufacturer Part Number: DK-DEV-2AGX260N
• Description: KIT DEV FPGA 2AGX260 W/6.375G TX
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX260N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2696

2–22
Arria II GX FPGA Clock Outputs
Figure 2–7. Arria II GX FPGA Development Board, 6G Edition Clock Outputs
Table 2–20. Arria II GX FPGA Development Board, 6G Edition Clock Outputs
Arria II GX FPGA Development Board, 6G Edition Reference Manual
Samtec HSMC HSMA_CLKOUT0
Samtec HSMC HSMA_CLKOUT_P1
Samtec HSMC HSMA_CLKOUT_P2
Samtec HSMC HSMB_CLKOUT0
Connector
SMA
7 6 5 4 3 2 1 0
SMA
HSMB_CLKOUT_P[2] / N[2]
(Differential SSTL-15)
CLKOUT_SMA
HSMA_CLKOUT_N1
HSMA_CLKOUT_N2
DDR3_CLK_P/N
Schematic Signal Name
CLOCK_SMA
Figure 2–7
outputs.
Table 2–20
Edition.
(2.5 V)
(LVDS)
HSMA_CLKOUT0
HSMA_CLKOUT_P[1] / N[1]
(2.5 V)
shows the Arria II GX FPGA development board, 6G Edition clock
lists the clock outputs for the Arria II GX FPGA development board, 6G
(LVDS)
PLL 2
PLL 1
Q 3
6 B
AG30
HSMA_CLKOUT_P[2] / N[2]
W12
AD7
AD6
P10
V12
F23
Pin
EP2AGX260FF35
Q 2
6 A
PLL
(LVDS)
5
LVDS or 2.5-V
LVDS or 2.5-V
I/O Standard
2.5-V
2.5-V
2.5-V
PLL
Q 1
5 A
6
7 6 5 4 3 2 1 0
PLL 3
PLL 4
FPGA CMOS output or general purpose I/O (GPIO)
FPGA CMOS output or GPIO
LVDS output or two 2.5-V CMOS outputs.
LVDS output or two 2.5-V CMOS outputs.
FPGA CMOS output or GPIO
Q 0
5 B
(Differential SSTL-18)
DDR2_CLK_P/N[1:0]
Description
HSMB_CLKOUT0
© July 2010 Altera Corporation
(2.5 V)
Chapter 2: Board Components
Clock Circuitry