MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 57
![BOARD DEV FOR I.MX35](/photos/37/58/375859/imx35_bd_sml.jpg)
MCIMX35WPDKJ
Manufacturer Part Number
MCIMX35WPDKJ
Description
BOARD DEV FOR I.MX35
Manufacturer
Freescale Semiconductor
Series
i.MX35r
Type
MPUr
Datasheets
1.MCIMX35WPDKJ.pdf
(148 pages)
2.MCIMX35WPDKJ.pdf
(2 pages)
3.MCIMX35WPDKJ.pdf
(10 pages)
Specifications of MCIMX35WPDKJ
Contents
Module and Misc Hardware
Processor To Be Evaluated
i.MX35
Processor Series
i.MX35
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, CAN, JTAG
Core
ARM11
For Use With/related Products
i.MX35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Freescale Semiconductor
No.
87
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91
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
bl = bit length
wl = word length
wr = word length relative
SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
Periodically sampled and not 100% tested.
SCKT rising edge to FST out (wr) high
SCKT rising edge to FST out (wr) low
SCKT rising edge to FST out (wl) high
SCKT rising edge to FST out (wl) low
SCKT rising edge to data out enable from high
impedance
SCKT rising edge to data out valid
SCKT rising edge to data out high impedance
FST input (bl, wr) setup time before SCKT falling edge
FST input (wl) setup time before SCKT falling edge
FST input hold time after SCKT falling edge
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Characteristics
Table 43. Enhanced Serial Audio Interface Timing (continued)
1,2
5
5
67
5
Symbol
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Expression
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
Min.
18.0
18.0
2.0
2.0
4.0
5.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max. Condition
20.0
10.0
22.0
12.0
19.0
20.0
10.0
22.0
17.0
18.0
13.0
21.0
16.0
9.0
—
—
—
—
—
—
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
57
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